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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP93CS32F датащи(PDF) 169 Page - Toshiba Semiconductor |
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TMP93CS32F датащи(HTML) 169 Page - Toshiba Semiconductor |
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169 / 180 page  TMP93CS32 2004-02-10 93CS32-167 (7) Serial channel control Symbol Name Address 7 6 5 4 3 2 1 0 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 R (Receiving)/W (Transmission) SC0BUF Serial channel 0 buffer register 50H (Prohibit RMW) Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Cleared to 0 by reading) R/W undefined 0 0 0 0 0 0 0 1: Error SC0CR Serial channel 0 control register 51H Receiving data bit8 Parity 0: Odd 1: Even 1: Parity enable Overrun Parity Framing 0: SCLK0 1: SCLK0 1: Input SCLK0 pin TB8 CTSE0 RXE WU SM1 SM0 SC1 SC0 R/W Undefined 0 0 0 0 0 0 0 SC0MOD Serial channel 0 mode control register 52H Transmisson data bit8 1: CTS0 enable 1: Receive enable 1: Wake up enable 00: I/O interface 01: UART 7-bit 10: UART 8-bit 11: UART 9-bit 00: TO2 trigger 01: Baud rate generator 0 10: Internal clock φ1 11: External clock SCLK0 − BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R/W R/W 0 0 0 0 0 0 0 BR0CR Baud rate 0 control register 53H Fix at ”0” 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0000: 16 divisions 0001 to 1 to 15 divisions 1111 RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 RB1 RB0 TB0 R (Receiving)/W (Transmission) SC1BUF Serial channel 1 buffer register 54H (Prohibit RMW) Undefined RB8 EVEN PE OERR PERR FERR SCLKS IOC R R/W R (Cleared to 0 by reading.) R/W Undefined 0 0 0 0 0 0 0 1: Error SC1CR Serial channel 1 control register 55H Receiving data bit8 Parity 0: Odd 1: Even 1: Parity enable Overrun Parity Framing 0: SCLK1 1: SCLK1 1: Input SCLK1 pin TB8 CTSE1 RXE WU SM1 SM0 SC1 SC0 R/W undefined 0 0 0 0 0 0 0 SC1MOD Serial channel 1 mode control register 56H Transmisson data bit8 1: CTS1 enable 1: Receive enable 1: Wake up enable 00: I/O interface 01: UART 7-bit 10: UART 8-bit 11: UART 9-bit 00: TO2 trigger 01: Baud rate generator 1 10: Internal clock φ1 11: External clock SCLK1 − BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 R/W R/W 0 0 0 0 0 0 0 BR1CR Baud rate 1 control register 57H Fix at ”0” 00: φT0 01: φT2 10: φT8 11: φT32 Set frequency divisor 0000: 16 divisions 0001 to 1 to 15 divisions 1111 − − ODE63 ODE60 R/W 0 0 0 0 ODE Serial open drain enable 58H (Note) Always write “0”. 1: P63 open drain 1: P60 open drain |
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