PM7366-PI datasheet(188/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

175

before triggering the write. The FIFO pointer value can be any one of the block numbers

provisioned, by indirect block write operations, to form the circular buffer.

DELIN:

The indirect delineate enable bit (DELIN) configures the HDLC processor to perform flag

sequence insertion and bit stuffing on the outgoing data stream. The delineate enable bit to

be written to the channel provision RAM, in an indirect channel write operation, must be set up

in this register before triggering the write. When DELIN is set high, flag sequence insertion,

bit stuffing and ,optionally, CRC generation is performed on the outgoing HDLC data stream.

When DELIN is set low, the HDLC processor does not perform any processing (flag sequence

insertion, bit stuffing nor CRC generation) on the outgoing stream. DELIN reflects the value

written until the completion of a subsequent indirect channel read operation.

IDLE:

The interframe time fill bit (IDLE) configures the HDLC processor to use flag bytes or HDLC

idle as the interframe time fill between HDLC packets. The value of IDLE to be written to the

channel provision RAM, in an indirect channel write operation, must be set up in this register

before triggering the write. When IDLE is set low, the HDLC processor uses flag bytes as the

interframe time fill. When IDLE is set high, the HDLC processor uses HDLC idle (all one's bit

with no bit-stuffing pattern is transmitted) as the interframe time fill. IDLE reflects the value

written until the completion of a subsequent indirect channel read operation.

CRC[1:0]:

The CRC algorithm (CRC[1:0]) configures the HDLC processor to perform CRC generation

on the outgoing HDLC data stream. The value of CRC[1:0] to be written to the channel

provision RAM, in an indirect channel write operation, must be set up in this register before

triggering the write. CRC[1:0] is ignored when DELIN is low. CRC[1:0] reflects the value

written until the completion of a subsequent indirect channel read operation.

Table 24 – CRC[1:0] Settings

CRC[1]

CRC[0]

Operation

No CRC

CRC-CCITT

CRC-32

Reserved

PROV:

The indirect provision enable bit (PROV) reports the channel provision enable flag read from

the channel provision RAM after an indirect channel read operation has completed. The

provision enable flag to be written to the channel provision RAM, in an indirect write operation,

must be set up in this register before triggering the write. When PROV is set high, the HDLC

processor will service requests for data from the TCAS block. When PROV is set low, the

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