PM7366-PI datasheet(26/286 Pages) PMC

26 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin No.

Pin Name

Type

-PI

-BI

Function

TCLK[0]

TCLK[1]

TCLK[2]

TCLK[3]

TCLK[4]

TCLK[5]

TCLK[6]

TCLK[7]

Input

L19

L17

M19

N19

N18

P19

P18

R19

The transmit line clock signals (TCLK[7:0]) contain

the transmit clocks for the 8 independently timed

links. Processing of the transmit links is on a priority

basis, in descending order from TCLK[0] to TCLK[7].

Therefore, the highest rate link should be connected

to TCLK[0] and the lowest to TCLK[7]. TD[7:0] is

updated on the falling edge of the corresponding

TCLK[7:0] clock.

For channelised T1 or E1 links, TCLK[n] must be

gapped during the framing bit (for T1 interfaces) or

during time-slot 0 (for E1 interfaces) of the TD[n]

stream. The FREEDM-8 uses the gapping

information to determine the time-slot alignment in

the transmit stream.

For unchannelised links, TCLK[n] must be externally

gapped during the bits or time-slots that are not part

of the transmission format payload (i.e. not part of the

HDLC packet).

TCLK[7:3] is nominally a 50% duty cycle clock

between 0 and 10 MHz. TCLK[2:0] is nominally a

50% duty cycle clock between 0 and 52 MHz. Typical

values for TCLK[7:0] include 1.544 MHz (for T1 links)

and 2.048 MHz (for E1 links).

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