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PM7366-PI датащи(PDF) 88 Page - PMC-Sierra, Inc |
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PM7366-PI датащи(HTML) 88 Page - PMC-Sierra, Inc |
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88 / 286 page ![]() RELEASED PM7366 FREEDM-8 DATA SHEET PMC-1970930 ISSUE 4 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 75 PCI Offset Register 0x484 - 0x49C TCAS Link #1 to Link #7 Configuration 0x4A0 - 0x4FC TCAS Reserved 0x500 PMON Status 0x504 PMON Receive FIFO Overflow Count 0x508 PMON Transmit FIFO Underflow Count 0x50C PMON Configurable Count #1 0x510 PMON Configurable Count #2 0x514 - 0x51C PMON Reserved 0x520 - 0x7FC Reserved The following PCI configuration registers are implemented by the PCI Interface. These registers can only be accessed when the PCI Interface is a target and a configuration cycle is in progress as indicated using the IDSEL input. Table 15 – PCI Configuration Register Memory Map PCI Offset Register 0x00 Vendor Identification/Device Identification 0x04 Command/Status 0x08 Revision Identifier/Class Code 0x0C Cache Line Size/Latency Timer/Header Type/BIST 0x10 CBI Memory Base Address Register 0x14 - 0x24 Unused Base Address Register 0x28 Reserved 0x2C Reserved 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT |
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