PM7366-PI datasheet(81/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

The partial packet buffer processor is divided into three sections: reader, writer and roamer. The

roamer is a time-sliced state machine which tracks each channel's FIFO buffer free space and

signals the writer to service a particular channel. The writer requests data from the TMAC block

and transfers packet data from the TMAC to the associated channel FIFO. The reader is a time-

sliced state machine which transfers the HDLC information from a channel FIFO to the HDLC

processor when the HDLC processor requests it. If a buffer under-run occurs for a channel, the

reader informs the HDLC processor and purges the rest of the packet.

Figure 15 – Partial Packet Buffer Structure

16 bytes

Partial Packet

Buffer RAM

Block 511

Block 0

Block 1

Block 2

Block 3

Block 511

Block 0

Block 1

Block 2

Block 3

Block

Pointer RAM

Block 200

0x03

0xC8

0x01

The writer and reader determine empty and full FIFO conditions using flags. Each block in the

partial packet buffer has an associated flag. The writer sets the flag after the block is written and

the reader clears the flag after the block is read. The flags are initialized (cleared) when the block

pointers are written using indirect block writes. The reader declares a channel FIFO under-run

whenever it tries to read data from a block without a set flag.

The FIFO algorithm of the partial packet buffer processor is based on per-channel software

programmable transfer size and free space trigger level. Instead of tracking the number of full

blocks in a channel FIFO, the processor tracks the number of empty blocks, called free space, as

well as the number of end of packets stored in the FIFO. Recording the number of empty blocks

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