PM7366-PI datasheet(93/286 Pages) PMC

93 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

However, the SERRI bit remains valid when interrupts are disabled and may be polled to

detect PCI system error events.

PERRE:

The parity error interrupt enable bit (PERRE) enables PCI parity error interrupts to the PCI

host. When PERRE is set high, data parity errors detected by the FREEDM-8 or parity errors

reported by a target will cause an interrupt to be generated on the PCIINTB output. Interrupts

are masked when PERRE is set low. However, the PERRI bit remains valid when interrupts

are disabled and may be polled to detect PCI parity error events.

RFCSEE:

The receive frame check sequence error interrupt enable bit (RFCSEE) enables receive FCS

error interrupts to the PCI host. When RFCSEE is set high, a mismatch between the received

FCS code and the computed CRC residue will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit

remains valid when interrupts are disabled and may be polled to detect receive FCS error

events.

RABRTE:

The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort interrupts to the

PCI host. When RABRTE is set high, receipt of an abort code (at least 7 contiguous 1's) will

cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when

RABRTE is set low. However, the RABRTI bit remains valid when interrupts are disabled and

may be polled to detect receive abort events.

RPFEE:

The receive packet format error interrupt enable bit (RPFEE) enables receive packet format

error interrupts to the PCI host. When RPFEE is set high, receipt of a packet that is longer

than the maximum specified in the RHDL Maximum Packet Length register, of a packet that is

shorter than 32 bits (CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned

will cause an interrupt to be generated on the PCIINTB output. Interrupts are masked when

RPFEE is set low. However, the RPFEI bit remains valid when interrupts are disabled and

may be polled to detect receive packet format error events.

RFOVRE:

The receive FIFO overrun error interrupt enable bit (RFOVRE) enables receive FIFO overrun

error interrupts to the PCI host. When RFOVRE is set high, attempts to write data into the

logical FIFO of a channel when it is already full will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when RFOVRE is set low. However, the RFOVRI bit

remains valid when interrupts are disabled and may be polled to detect receive FIFO overrun

events.

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