PM7366-PI datasheet(187/286 Pages) PMC

187 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

174

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

PROV

Bit 14

R/W

CRC[1]

Bit 13

R/W

CRC[0]

Bit 12

R/W

IDLE

Bit 11

R/W

DELIN

Bit 10

Unused

Bit 9

Unused

Bit 8

FPTR[8]

Bit 7

FPTR[7]

Bit 6

FPTR[6]

Bit 5

FPTR[5]

Bit 4

FPTR[4]

Bit 3

FPTR[3]

Bit 2

FPTR[2]

Bit 1

FPTR[1]

Bit 0

FPTR[0]

This register contains data read from the channel provision RAM after an indirect channel read

operation or data to be inserted into the channel provision RAM in an indirect channel write

operation.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

FPTR[8:0]:

The indirect FIFO block pointer (FPTR[8:0]) informs the partial packet buffer processor the

circular linked list of blocks to use for a FIFO for the channel. The FIFO pointer to be written

to the channel provision RAM, in an indirect write operation, must be set up in this register

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