PM7366-PI datasheet(11/286 Pages) PMC

11 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING ...................................................... 249

FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING.................................................... 249

FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING.................................................... 250

FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING.................................................... 250

FIGURE 28 – PCI READ CYCLE............................................................................................... 252

FIGURE 29 – PCI WRITE CYCLE............................................................................................. 253

FIGURE 30 – PCI TARGET DISCONNECT .............................................................................. 254

FIGURE 31 – PCI TARGET ABORT .......................................................................................... 254

FIGURE 32 – PCI BUS REQUEST CYCLE ............................................................................... 255

FIGURE 33 – PCI INITIATOR ABORT TERMINATION ............................................................. 255

FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE.......................................................................... 256

FIGURE 35 – PCI FAST BACK TO BACK ................................................................................. 258

FIGURE 36 – RECEIVE BERT PORT TIMING.......................................................................... 258

FIGURE 37 – TRANSMIT BERT PORT TIMING ....................................................................... 259

FIGURE 38 – RECEIVE LINK INPUT TIMING .......................................................................... 264

FIGURE 39 – BERT INPUT TIMING.......................................................................................... 264

FIGURE 40 – TRANSMIT LINK OUTPUT TIMING.................................................................... 265

FIGURE 41 – BERT OUTPUT TIMING...................................................................................... 266

FIGURE 42 – PCI INTERFACE TIMING.................................................................................... 267

FIGURE 43 – JTAG PORT INTERFACE TIMING...................................................................... 268

FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA)............................................. 270

FIGURE 45 – 272 PIN PLASTIC BALL GRID ARRAY (PBGA).................................................. 271

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