PM7366-PI datasheet(27/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin No.

Pin Name

Type

-PI

-BI

Function

TD[0]

TD[1]

TD[2]

TD[3]

TD[4]

TD[5]

TD[6]

TD[7]

Output

L20

L18

M20

M18

M17

P20

N17

R20

The transmit data signals (TD[7:0]) contains the

transmit data for the 8 independently timed links.

Processing of the transmit links is on a priority basis,

in descending order from TD[0] to TD[7]. Therefore,

the highest rate link should be connected to TD[0]

and the lowest to TD[7].

For channelised links, TD[n] contains the 24 (T1) or

31 (E1) time-slots that comprise the channelised link.

TCLK[n] must be gapped during the T1 framing bit

position or the E1 frame alignment signal (time-slot

0). The FREEDM-8 uses the location of the gap to

determine the channel alignment on TD[n].

For unchannelised links, TD[n] contains the HDLC

packet data. For certain transmission formats, TD[n]

may contain place holder bits or time-slots. TCLK[n]

must be externally gapped during the place holder

positions in the TD[n] stream. The FREEDM-8

supports a maximum data rate of 10 Mbit/s on an

individual TD[7:3] link and a maximum data rate of

52 Mbit/s on TD[2:0]

TD[7:0] is updated on the falling edge of the

corresponding TCLK[7:0] clock.

TBD

Input

W15

The transmit BERT data signal (TBD) contains the

transmit bit error rate test data. When the TBERTEN

bit in the BERT Control register is set high, the data

on TBD is transmitted on the selected one of the

transmit data signals (TD[7:0]). TBD is sampled on

the rising edge of TBCLK.

TBCLK

Tristate

Output

Y16

The transmit BERT clock signal (TBCLK) contains the

transmit bit error rate test clock. TBCLK is a buffered

version of the selected one of the transmit clock

signals (TCLK[7:0]). TBCLK may be tri-stated by

setting the TBEN bit in the FREEDM-8 Master BERT

Control register low.

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