PM7366-PI datasheet(94/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RPQSFE:

The receive packet descriptor small buffer free queue cache read interrupt enable bit

(RPQSFE) enables receive packet descriptor small free queue cache read interrupts to the

PCI host. When RPQSFE is set high, reading a programmable number of RPDR blocks from

the RPDR Small Buffer Free Queue will cause an interrupt to be generated on the PCIINTB

output. Interrupts are masked when RPQSFE is set low. However, the RPQSFI bit remains

valid when interrupts are disabled and may be polled to detect RPDR small buffer free queue

cache read events.

RPQLFE:

The receive packet descriptor large buffer free queue cache read interrupt enable bit

(RPQLFE) enables receive packet descriptor large free queue cache read interrupts to the

PCI host. When RPQLFE is set high, reading a programmable number of RPDR blocks from

the RPDR Large Buffer Free Queue will cause an interrupt to be generated on the PCIINTB

output. Interrupts are masked when RPQLFE is set low. However, the RPQLFI bit remains

valid when interrupts are disabled and may be polled to detect RPDR large buffer free queue

cache read events.

RPQRDYE:

The receive packet descriptor ready queue write interrupt enable bit (RPQRDYE) enables

receive packet descriptor ready queue write interrupts to the PCI host. When RPQRDYE is

set high, writing a programmable number of RPDRs to the RPDR Ready Queue will cause an

interrupt to be generated on the PCIINTB output. Interrupts are masked when RPQRDYE is

set low. However, the RPQRDYI bit remains valid when interrupts are disabled and may be

polled to detect RPDR ready queue write events.

RPDFQEE:

The receive packet descriptor free queue error interrupt enable bit (RPDFQEE) enables

receive packet descriptor free queue error interrupts to the PCI host. When RPDFQEE is set

high, attempts to retrieve an RPDR when both the large buffer and small buffer free queues

are empty will cause an interrupt to be generated on the PCIINTB output. Interrupts are

masked when RPDFQEE is set low. However, the RPDFQEI bit remains valid when interrupts

are disabled and may be polled to detect RPDR free queue empty error events.

RPDRQEE:

The receive packet descriptor ready queue error interrupt enable bit (RPDRQEE) enables

receive packet descriptor ready queue error interrupts to the PCI host. When RPDRQEE is

set high, attempts to write an RPDR when ready queue is ready full will cause an interrupt to

be generated on the PCIINTB output. Interrupts are masked when RPDRQEE is set low.

However, the RPDRQEI bit remains valid when interrupts are disabled and may be polled to

detect RPDR ready queue full error events.

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