PM7366-PI datasheet(192/286 Pages) PMC

192 / 286 page

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

179

Bit

Type

Function

Default

Bit 31 to

Bit 16

Unused

XXXXH

Bit 15

R/W

TRANS

Bit 14

Unused

Bit 13

Unused

Bit 12

Unused

Bit 11

R/W

LEVEL[3]

Bit 10

R/W

LEVEL[2]

Bit 9

R/W

LEVEL[1]

Bit 8

R/W

LEVEL[0]

Bit 7

R/W

FLAG[2]

Bit 6

R/W

FLAG[1]

Bit 5

R/W

FLAG[0]

Bit 4

Unused[

Bit 3

Unused

Bit 2

R/W

XFER[2]

Bit 1

R/W

XFER[1]

Bit 0

R/W

XFER[0]

This register contains data read from the channel provision RAM after an indirect read operation

or data to be inserted into the channel provision RAM in an indirect write operation.

Note

This register is not byte addressable. Writing to this register modifies all the bits in the register.

Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all

four byte enables are negated, no access is made to this register.

XFER[2:0]:

The indirect channel transfer size (XFER[2:0]) specifies the amount of data the partial packet

processor requests from the TMAC block. The channel transfer size to be written to the

channel provision RAM, in an indirect write operation, must be set up in this register before

triggering the write. When the channel FIFO free space reaches or exceeds the limit

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