PM7366-PI datasheet(49/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

of the channel FIFOs are monitored in a round-robin fashion. Requests are made to the Receive

DMA Controller block (RMAC) to transfer, to the PCI host memory, data in channel FIFOs with

depths exceeding their associated threshold.

9.3.1

HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 128 independent

channels. The state vector and provisioning information for each channel is stored in a RAM.

Whenever new channel data arrives, the appropriate state vector is read from the RAM,

processed and written back to the RAM. The HDLC state-machine can be configured to perform

flag delineation, bit de-stuffing, CRC verification and length monitoring. The resulting HDLC data

and status information is passed to the partial packet buffer processor to be stored in the

appropriate channel FIFO buffer.

The configuration of the HDLC processor is accessed using indirect channel read and write

operations. When an indirect operation is performed, the information is accessed from RAM

during a null clock cycle generated by the upstream Receive Channel Assigner block (RCAS).

Writing new provisioning data to a channel resets the channel's entire state vector.

9.3.2

Partial Packet Buffer Processor

The partial packet buffer processor controls the 8 Kbyte partial packet RAM which is divided into

16 byte blocks. A block pointer RAM is used to chain the partial packet blocks into circular

channel FIFO buffers. Thus, non-contiguous sections of the RAM can be allocated in the partial

packet buffer RAM to create a channel FIFO. System software is responsible for the assignment

of blocks to individual channel FIFOs. Figure 3 shows an example of three blocks (blocks 1, 3,

and 200) linked together to form a 48 byte channel FIFO.

The partial packet buffer processor is divided into three sections: writer, reader and roamer. The

writer is a time-sliced state machine which writes the HDLC data and status information from the

HDLC processor into a channel FIFO in the packet buffer RAM. The reader transfers channel

FIFO data from the packet buffer RAM to the downstream Receive DMA Controller block (RMAC).

The roamer is a time-sliced state machine which tracks channel FIFO buffer depths and signals

the reader to service a particular channel. If a buffer over-run occurs, the writer ends the current

packet from the HDLC processor in the channel FIFO with an over-run flag and ignores the rest of

the packet.

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