PM7366-PI datasheet(24/286 Pages) PMC

24 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PIN DESCRIPTION

Table 1 – Line Side Interface Signals (36)

Pin No.

Pin Name

Type

-PI

-BI

Function

RCLK[0]

RCLK[1]

RCLK[2]

RCLK[3]

RCLK[4]

RCLK[5]

RCLK[6]

RCLK[7]

Input

H17

F20

F18

E19

E18

D19

D18

D16

The receive line clock signals (RCLK[7:0]) contain the

recovered line clock for the 8 independently timed

links. Processing of the receive links is on a priority

basis, in descending order from RCLK[0] to RCLK[7].

Therefore, the highest rate link should be connected

to RCLK[0] and the lowest to RCLK[7]. RD[7:0] is

sampled on the rising edge of the corresponding

RCLK[7:0] clock.

For channelised T1 or E1 links, RCLK[n] must be

gapped during the framing bit (for T1 interfaces) or

during time-slot 0 (for E1 interfaces) of the RD[n]

stream. The FREEDM-8 uses the gapping

information to determine the time-slot alignment in

the receive stream. RCLK[7:0] is nominally a 50%

duty cycle clock of 1.544 MHz for T1 links and 2.048

MHz for E1 links.

For unchannelised links, RCLK[n] must be externally

gapped during the bits or time-slots that are not part

of the transmission format payload (i.e. not part of the

HDLC packet). RCLK[2:0] is nominally a 50% duty

cycle clock between 0 and 52 MHz. RCLK[7:3] is

nominally a 50% duty cycle clock between 0 and 10

MHz.

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