PM7366-PI datasheet(48/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Thus, simultaneous requests from RD[m] will be serviced ahead of RD[n], if m < n. When there

are no pending requests, the priority encoder generates an idle cycle. In addition, once every

fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests are serviced.

This cycle is used by the channel assigner downstream for host microprocessor accesses to the

provisioning RAMs.

9.2.3

Channel Assigner

The channel assigner block determines the channel number of the data byte currently being

processed. The block contains a 256 word channel provision RAM. The address of the RAM is

constructed from concatenating the link number and the time-slot number of the current data byte.

The fields of each RAM word include the channel number and a time-slot enable flag. The time-

slot enable flag labels the current time-slot as belonging to the channel indicted by the channel

number field.

9.2.4

Loopback Controller

The loopback controller block implements the channel based diagnostic loopback function. Every

valid data byte belonging to a channel with diagnostic loopback enabled from the Transmit HDLC

Processor / Partial Packet Buffer block (THDL) is written into a 64 word FIFO. The loopback

controller monitors for an idle time-slot or a time-slot carrying a channel with diagnostic loopback

enabled. If either conditions hold, the current data byte is replaced by data retrieved from the

loopback data FIFO.

9.3

Receive HDLC Processor / Partial Packet Buffer

The Receive HDLC Processor / Partial Packet Buffer block (RHDL) processes up to 128

synchronous transmission HDLC data streams. Each channel can be individually configured to

perform flag sequence detection, bit de-stuffing and CRC-CCITT or CRC-32 verification. The

packet data is written into the partial packet buffer. At the end of a frame, packet status including

CRC error, octet alignment error and maximum length violation are also loaded into the partial

packet buffer. Alternatively, a channel can be provisioned as transparent, in which case, the

HDLC data stream is passed to the partial packet buffer processor verbatim.

There is a natural precedence in the alarms detectable on a receive packet. Once a packet

exceeds the programmable maximum packet length, no further processing is performed on it.

Thus, octet alignment detection, FCS verification and abort recognition are squelched on packets

with a maximum length violation. An abort indication squelches octet alignment detection,

minimum packet length violations, and FCS verification. In addition, FCS verification is only

performed on packets that do not have octet alignment errors, in order to allow the RHDL to

perform CRC calculations on a byte-basis.

The partial packet buffer is an 8 Kbyte RAM that is divided into 16-byte blocks. Each block has an

associated pointer which points to another block. A logical FIFO is created for each provisioned

channel by programming the block pointers to form a circular linked list. A channel FIFO can be

assigned a minimum of 3 blocks (48 bytes) and a maximum of 512 blocks (8 Kbytes). The depth

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