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PM7366-PI датащи(PDF) 124 Page - PMC-Sierra, Inc

номер детали PM7366-PI
подробное описание детали  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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производитель  PMC [PMC-Sierra, Inc]
домашняя страница  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI датащи(HTML) 124 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
111
Register 0x184 - 0x188 : RCAS Link #1 to #2 Configuration
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
Unused
X
Bit 5
Unused
X
Bit 4
Unused
X
Bit 3
Unused
X
Bit 2
R/W
BSYNC
0
Bit 1
R/W
E1
0
Bit 0
R/W
CEN
0
This register set configures operational modes of receive link #1 to link #2 (RD[n] / RCLK[n];
where 1
£ n £ 2).
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
CEN:
The channelise enable bit (CEN) configures the corresponding receive link for channelised
operation. RCLK[n] is held quiescent during the T1 framing bit and during the E1 framing
bytes. The data bit on RD[n] clocked in by the first rising edge of RCLK[n] after an extended
quiescent period is considered to be the most significant bit of time-slot 1. When CEN is set



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