PM7366-PI datasheet(123/286 Pages) PMC

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PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

110

non-data bytes. The choice between treating all data bits as a contiguous stream with

arbitrary byte alignment or byte aligned to gaps in RCLK[0] is controlled by the BSYNC bit.

E1:

The E1 frame structure select bit (E1) configures receive link #0 for channelised E1 operation

when CEN is set high. RCLK[0] is held quiescent during the FAS and NFAS framing bytes.

The data bit on RD[0] associated with the first rising edge of RCLK[0] after an extended

quiescent period is considered to be the most significant bit of time-slot 1. Link data is

present at time-slots 1 to 31. When E1 is set low and CEN is set high, receive link #0 is

configured for channelised T1 operation. RCLK[0] is held quiescent during the framing bit.

The data bit on RD[0] associated with the first rising edge of RCLK[0] after an extended

quiescent period is considered to be the most significant bit of time-slot 1. Link data is

present at time-slots 1 to 24. E1 is ignored when CEN is set low.

BSYNC:

The byte synchronisation enable bit (BSYNC) controls the interpretation of gaps in RCLK[0]

when link #0 is in unchannelised mode (CEN set low). When BSYNC is set high, the data bit

on RD[0] clocked in by the first rising edge of RCLK[0] after an extended quiescent period is

considered to be the most significant bit of a data byte. When BSYNC is set low, gaps in

RCLK[0] carry no special significance. BSYNC is ignore when CEN is set high.

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