PM7366-PI datasheet(103/286 Pages) PMC

номер детали	PM7366-PI

подробное описание детали	FRAME ENGINE AND DATA LINK MANAGER

PDF	286 Pages

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производитель	PMC [PMC-Sierra, Inc]

домашняя страница	http://www.pmc-sierra.com

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103 / 286 page

RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RLGA[0]:

The receive link group #0 active bit (RLGA[0]) monitors for transitions on the RD[3:0] and

RCLK[3:0] inputs. RLGA[0] is set high when each of RD[3:0] has been sampled low and

sampled high by rising edges of the corresponding RCLK[3:0] inputs, and is set low when this

RLGA[1]:

The receive link group #1 active bit (RLGA[1]) monitors for transitions on the RD[7:4] and

RCLK[7:4] inputs. RLGA[1] is set high when each of RD[7:4] has been sampled low and

sampled high by rising edges of the corresponding RCLK[7:4] inputs, and is set low when this

TLGA[0]:

The transmit link group #0 active bit (TLGA[0]) monitors for low to high transitions on the

TCLK[3:0] inputs. TLGA[0] is set high when rising edges have been observed on all the

signals on the TCLK[3:0] inputs, and is set low when this register is read.

TLGA[1]:

The transmit link group #1 active bit (TLGA[1]) monitors for low to high transitions on the

TCLK[7:4] inputs. TLGA[1] is set high when rising edges have been observed on all the

signals on the TCLK[7:4] inputs, and is set low when this register is read.

PM7366-PI датащи(PDF) 103 Page - PMC-Sierra, Inc