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7.10.5.1.2 CPSW3G RMII Timing

Table 7-29, Table 7-30, Figure 7-27, Table 7-31, Figure 7-28, Table 7-32, and Figure 7-29 present timing

conditions, requirements, and switching characteristics for CPSW3G RMII.

Table 7-29. CPSW3G RMII Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

VDD(1) = 1.8V

0.18

0.54

V/ns

VDD(1) = 3.3V

0.4

1.2

V/ns

OUTPUT CONDITIONS

Output load capacitance

(1)

VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see

POWER column of the Pin Attributes table.

Table 7-30. RMII[x]_REF_CLK Timing Requirements – RMII Mode

see Figure 7-27

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII1

tc(REF_CLK)

Cycle time, RMII[x]_REF_CLK

19.999

20.001

RMII2

tw(REF_CLKH)

Pulse Duration, RMII[x]_REF_CLK High

RMII3

tw(REF_CLKL)

Pulse Duration, RMII[x]_REF_CLK Low

RMII[x]_REF_CLK

RMII2

RMII3

RMII1

Figure 7-27. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode

Table 7-31. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode

see Figure 7-28

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

RMII4

tsu(RXD-REF_CLK)

Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK

tsu(CRS_DV-REF_CLK)

Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK

tsu(RX_ER-REF_CLK)

Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK

RMII5

th(REF_CLK-RXD)

Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK

th(REF_CLK-CRS_DV)

Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK

th(REF_CLK-RX_ER)

Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK

RMII4

RMII5

RMII[x]_

REF CLK

RMII[x]_RXD[1:0], RMII[x]_CRS_DV,

RMII[x]_RX_ER

Figure 7-28. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII

Mode

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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