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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM62A7 датащи(PDF) 118 Page - Texas Instruments |
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AM62A7 датащи(HTML) 118 Page - Texas Instruments |
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118 / 238 page  7.10.5 Peripherals 7.10.5.1 CPSW3G For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding subsections within Signal Descriptions and Detailed Description sections. 7.10.5.1.1 CPSW3G MDIO Timing Table 7-26, Table 7-27, Table 7-28, and Figure 7-26 present timing conditions, requirements, and switching characteristics for CPSW3G MDIO. Table 7-26. CPSW3G MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 0 5 ns td(Trace Mismatch Delay) Propagation delay mismatch across all traces 1 ns Table 7-27. CPSW3G MDIO Timing Requirements see Figure 7-26 NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 45 ns MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 7-28. CPSW3G MDIO Switching Characteristics see Figure 7-26 NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -10 10 ns MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 7-26. CPSW3G MDIO Timing Requirements and Switching Characteristics AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 www.ti.com 118 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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