AM62A7 datasheet(106/238 Pages) TI1

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7.10.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching

characteristics for clock signals.

Table 7-18. Clock Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

5 ns ≤ tc < 8 ns

5 pF

8 ns ≤ tc < 20 ns

10 pF

20 ns ≤ tc

30 pF

Table 7-19. Clock Timing Requirements

see Figure 7-14

NO.

MIN

MAX UNIT

CLK1

tc(EXT_REFCLK1)

Cycle time minimum, EXT_REFCLK1

CLK2

tw(EXT_REFCLK1H)

Pulse Duration, EXT_REFCLK1 high

E*0.45(1)

E*0.55(1)

CLK3

tw(EXT_REFCLK1L)

Pulse Duration, EXT_REFCLK1 low

E*0.45(1)

E*0.55(1)

CLK1

tc(MCU_EXT_REFCLK0)

Cycle time minimum, MCU_EXT_REFCLK0

CLK2

tw(MCU_EXT_REFCLK0H)

Pulse Duration, MCU_EXT_REFCLK0 high

F*0.45(2)

F*0.55(2)

CLK3

tw(MCU_EXT_REFCLK0L)

Pulse Duration, MCU_EXT_REFCLK0 low

F*0.45(2)

F*0.55(2)

CLK1

tc(AUDIO_EXT_REFCLK0)

Cycle time minimum, AUDIO_EXT_REFCLK0

CLK2

tw(AUDIO_EXT_REFCLK0H)

Pulse Duration, AUDIO_EXT_REFCLK0 high

G*0.45(3)

G*0.55(3)

CLK3

tw(AUDIO_EXT_REFCLK0L)

Pulse Duration, AUDIO_EXT_REFCLK0 low

G*0.45(3)

G*0.55(3)

CLK1

tc(AUDIO_EXT_REFCLK1)

Cycle time minimum, AUDIO_EXT_REFCLK1

CLK2

tw(AUDIO_EXT_REFCLK1H)

Pulse Duration, AUDIO_EXT_REFCLK1 high

H*0.45(4)

H*0.55(4)

CLK3

tw(AUDIO_EXT_REFCLK1L)

Pulse Duration, AUDIO_EXT_REFCLK1 low

H*0.45(4)

H*0.55(4)

(1)

E = EXT_REFCLK1 cycle time in ns.

(2)

F = MCU_EXT_REFCLK0 cycle time in ns.

(3)

G = AUDIO_EXT_REFCLK0 cycle time in ns.

(4)

H = AUDIO_EXT_REFCLK1 cycle time in ns.

Input Clock

CLK1

CLK2

CLK3

Figure 7-14. Clock Timing Requirements

AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

www.ti.com

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