AM62A7 datasheet(153/238 Pages) TI1

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7.10.5.11.3 GPMC and NAND Flash — Asynchronous Mode

Table 7-67 and Table 7-68 present timing requirements and switching characteristics for GPMC and NAND Flash

— Asynchronous Mode.

Table 7-67. GPMC and NAND Flash Timing Requirements – Asynchronous Mode

see Figure 7-59

NO.

PARAMETER

DESCRIPTION

MODE

(4)

MIN

MAX

UNIT

133 MHz

GNF12

(1)

tacc(d)

Access time, input data GPMC_AD[15:0]

(3)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

(2)

(1)

The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2)

J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(3)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(4)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

Table 7-68. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode

see Figure 7-57, Figure 7-58, Figure 7-59 and Figure 7-60

NO.

PARAMETER

MODE

(4)

MIN

MAX UNIT

GNF0 tw(wenV)

Pulse duration, output write enable GPMC_WEn

valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

GNF1 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](2)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

B - 2

B + 2

GNF2 tw(cleH-wenV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE high to

output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

C - 2

C + 2

GNF3 tw(wenV-dV)

Delay time, output data GPMC_AD[15:0] valid to

output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

D - 2

D + 2

GNF4 tw(wenIV-dIV)

Delay time, output write enable GPMC_WEn

invalid to output data GPMC_AD[15:0] invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

E - 2

E + 2

GNF5 tw(wenIV-cleIV)

Delay time, output write enable GPMC_WEn

invalid to output lower-byte enable and command

latch enable GPMC_BE0n_CLE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

F - 2

F + 2

GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn

invalid to output chip select GPMC_CSn[i](2)

invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

G - 2

G + 2

GNF7 tw(aleH-wenV)

Delay time, output address valid and address latch

enable GPMC_ADVn_ALE high to output write

enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

C - 2

C + 2

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AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1

SPRSP77A – MARCH 2023 – REVISED AUGUST 2023

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