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PCA5010 датащи(PDF) 39 Page - NXP Semiconductors |
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PCA5010 датащи(HTML) 39 Page - NXP Semiconductors |
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39 / 112 page ![]() 1998 Nov 02 39 Philips Semiconductors Product specification Pager baseband controller PCA5010 6.14 Wake-up counter 6.14.1 FUNCTION The wake-up counter is intended to be used as protocol timer. It can be programmed to wake-up the processor when the protocol needs an action. Amongst others this may be: • Switching on the DC/DC converter at time 0 • Enabling the receiver at time 1 • Enabling the demodulator and clock recovery function at time 2 before relevant data is expected. The time to wake-up is defined as a 16-bit value containing the number of 9600 Hz ticks. The maximum time interval that can be spawn with one cycle then equals 6.8 s. The wake-up counter and it’s reload latch are supplied by VBAT and work independent of the 2 V supply. A reset to the microcontroller does not clear the wake-up counter control flags or the reload latch, but clears the reload register (see Fig.21). The counter is implemented as a 16-bit ripple down counter. It can be loaded from the wake-up reload latch by a signal from the processor. When the counter is loaded it automatically starts if the RUN signal is active. When the counter reaches zero the wake-up signal becomes active and may generate an interrupt. The wake-up signal automatically reloads the counter (modulo N counter). The counter is stopped when the RUN signal is written to logic 0. Auto reloading of the counter is also possible, when the DC/DC converter is not operating (i.e. VDD is below 1.8 V). The contents of the wake-up counter cannot be read by the processor. Reading WUC0 and WUC1 reflects the contents of the 16-bit wake-up register (set by the microcontroller). The interface between 2 and 1 V regions is implemented similar to the clock correction block. The sequence for writing values is identical (see Fig.16). Fig.21 Block diagram of wake-up counter. handbook, full pagewidth MGR122 1 STORE 9600 Hz internal SET FLAG SFR to microcontroller RESET with each OFF cycle SET CPL RUN LOAD WUP TEST Z1 Z0 WU0 to WU15 WU RELOAD LATCH (16-BIT) reload data WU COUNTER (16-BIT) & Interrupt ≥ 1 ≥ 1 reload VDD supply wake-up DC/DC converter VBAT supply CARRY RESET only on RESETIN |
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