PCA5010 datasheet(15/112 Pages) PHILIPS

15 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

6.6

I/O facilities

6.6.1

PORTS

The PCA5010 has 27 I/O lines treated as 27 individually

addressable bits or as four parallel 8-bit addressable ports.

Ports 0 and 2 are complete, Port 1 has only 7 and Port 3

has only 4 pins externally available. Ports 0, 1, 2 and 3

perform the following alternative functions:

Port 0 Is also used for external access, parallel OTP

programming mode and emulation (see Table 2 for

configuration details):

• Provides the multiplexed low-order address and

data bus for expanding the device with standard

memories and peripherals

• Provides access to the OTP data I/O lines in OTP

parallel programming mode.

Port 1 Used for a number of alternative functions (see

Table 3 for configuration details):

• Provides the inputs for the external interrupts

INT2/P1.0 to INT4/P1.2 and INT6/P1.4

• SCL/P1.6 and SDA/P1.7 for the I2C-bus interface

are real open-drain outputs; no other port

configurations are available

• RXD/P1.3 and TXD/P1.4 for the UART data input

and output.

Port 2 Is also used for external access, parallel OTP

programming mode and emulation (see Table 4 for

configuration details):

• Provides the high-order address bus when

expanding the device with external program

memory

• Allows control of the on-chip OTP parallel

programming mode.

Port 3 Pins are configured as strong push-pull outputs

(see Table 5 for configuration details).

The following alternative Port 3 functions are

available, but to avoid short-circuiting of the

mentioned port pins, the input signals cannot be

applied externally to the Port 3 pins. The alternative

function can only be stimulated via the respective

port output function:

• External interrupt request inputs INT0/P3.2 and

INT1/P3.3

• Counter inputs T0/P3.4 and T1/P3.5.

To enable a port pin alternative function, the port bit latch

in its SFR must contain a logic 1.

Each port consists of a latch (SFRs P0 to P3), an output

driver and input buffer. Standard ports have internal

pull-ups. Figure 6a shows that the strong transistor p1 is

turned on for only a short time after a LOW-to-HIGH

transition in the port latch. When on, it turns on p3 (a weak

pull-up) through the inverter IN1. This inverter and p3 form

a latch which holds the logic 1.

6.6.2

PORT I/O CONFIGURATION (OPTIONS)

I/O port output configurations are determined on-chip

according to one of the options shown in Fig.6. They

cannot be changed by software.

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