PCA5010 datasheet(44/112 Pages) PHILIPS

44 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

WDCON.2

−

unused

WDCON.1

−

unused

WDCON.0

Load watchdog timer with WD0 to WD3. Control signal from processor.

BIT

SYMBOL

FUNCTION

6.16.3

SAMPLE SEQUENCE TO RELOAD THE WATCHDOG

The sequence to reload the watchdog with 1 s is:

MOV WDCON, #80H; prepare condition

MOV WDCON, #01H; reload the timer.

6.17

2 or 4-FSK demodulator, ﬁlter and clock

recovery circuit

6.17.1

FUNCTION

The aim of the blocks demodulator and clock recovery

circuitry is to take the signal from the receiver, to format it

into symbols and to transfer it to the processor. The two

blocks use the 76.8 kHz clock.

The demodulator decodes the incoming signal and

generates a sequence of NRZ data. This data is fed to the

clock recovery block which regenerates the

synchronization clock. This clock is used to sample and to

shift the symbols into the register DMD3. Each block is

enabled separately. To save power, the functions should

be disabled whenever not needed.

6.17.1.1

Demodulator and ﬁlter

The demodulator can operate both with 2-level or 4-level

FSK input signals (selectable by means of bit LEV).

For both types of input signals the so called demodulator,

filter and direct modes are allowed. The operation mode is

selected on the basis of M bit and BF bit.

In the demodulator mode (M = 0 and BF = X) the I and Q

signals are decoded according to Table 36.

Operating in this mode, an offset compensation can be

performed and the calculated offset value is stored into

used by the processor to adjust the analog AFC output

voltage.

The offset coding is given in Table 37.

The performance of the demodulator for the different baud

rates in 2L mode is shown in Fig.24 and for 4L mode in

Fig.25. The graphs show the Bit Error Rate (BER) as a

function of Eb/No (ratio of signal energy per bit to average

noise power per unit bandwidth).

Both the filter and direct modes are intended for

application with an external demodulator. In this case NRZ

data is fed to the I and Q pins. In the 4-FSK case, the MSB

is at pin I and the LSB is at pin Q. In the 2-FSK situation,

only the I pin is used while pin Q must be connected to

VSS. In these two modes, the offset calculation and

compensation cannot be performed.

In the filter mode (M = 1 and BF = 0), the data is filtered

and then sent to the clock recovery. The filter

characteristics of the implemented filter are shown in

Fig.26.

In the direct mode (M = 1 and BF = 1), no function of the

demodulator is performed. Consequently there is no

filtering on the data which is sent directly to the clock

recovery.

Table 36 Modulation coding

Table 37 Offset coding (2s complement)

FREQUENCY

(Hz)

2-FSK

4-FSK

+4800

+1600

−1600

−4800

OFFSET (Hz)

CODE (AVG6 TO AVG0)

−9450

0111111

−9300

0111110

...

−300

0000010

−150

0000001

0000000

150

1111111

300

1111110

...

9300

1000001

9450

1000000

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