PCA5010 datasheet(86/112 Pages) PHILIPS

86 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

Notes

1. DC/DC converter configured with inductor of L = 470

µH, SRL = 5 Ω, input capacitance of Ci = 4.7 µF, ESR = 0.5 Ω,

VDD output capacitor Co = 4.7 µF, ESR = 0.5 Ω, RBAT <1 Ω.

2. This parameter is not tested during production; it is guaranteed by design.

3. This parameter depends on external components.

4. At high load or low battery voltage the inductor charge time can be extended to a full XTL1 period, while the minimum

inductor discharge time is a half XTL1 period.

5. The execution time is strongly dependant on command type and addressing mode (see also Table 60).

ZIF (I and Q) demodulator

foffset

offset from 0 frequency

note 2

−−

kHz

t(ENA-AVG)

ENA to valid AVG value

3 kHz offset; note 2

−−

100

tENB

ENB to valid

demodulator output

note 2

−−

symbol

duration

tENC

ENB to correct recovered

clock

note 2

phase error curves apply (see Fig.27)

All outputs

tr,f

rise and fall times for

outputs

CL =20pF

−

Open-drain pins SDA and SCL (P1.7 and P1.6)

noise suppression ﬁlter

−

∆V/∆t

slope for the falling edge

RL =20kΩ; CL = 50 pF;

VDD = 2.2 V

−

ns/V

dI/dt

slope for both edges

RL =20kΩ; CL =50pF

−

250

−µA/ns

Io(sink)(swL)

dynamic output sink

current during switching

low (Miller compensated)

VDD = 2.2 V; RL =20kΩ;

CL =50pF

−

OTP programming characteristics

VSU;PP

VPP set-up time

−−

µs

tW(prog)

program pulse width

100

−−

µs

tW(prog)(sec)

program pulse security

bits

200

−−

µs

tW(prog)(rec)

program pulse recover

time

−−

µs

AFC-DAC

tstart(DAC)

start-up time disabled

DAC to stable output for

code 111111

note 2

−

100

µs

PSRR

power supply ripple

rejection (VDD -> DAC)

−

tslew

slew time for analog

output from 10 to 90%

for a voltage step of 1 V

code 010000 <-> 110000

−

2.5

−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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