PCA5010 datasheet(46/112 Pages) PHILIPS

46 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

Fig.26 Filter characteristics in direct filter mode.

handbook, full pagewidth

−40

102

103

104

MGR341

−30

−20

−10

amplitude

(dB)

f (Hz)

1600 1200

2400 3125 3200

6.17.1.2

Clock recovery

The clock recovery regenerates the synchronization clock

using the edges of the incoming NRZ data. When the NRZ

data have no edges for a long time, the synchronization is

maintained by means of the correction information from

the clock correction block.

While the clock recovery is disabled, the momentary

phase of the recovered clock is frozen. If the clock

recovery is enabled at the same relative position within

one bit, where it was disabled, then the recovered clock

phase will be correct immediately.

The recovered clock is used to sample and shift to left into

an internal register one bit each symbol period in 2-FSK

and two bits in 4-FSK. The symbol period is determined by

bits BD2 to BD0. On the basis of BD bits the demodulator

filter length is also set.

In the clock recovery, a pulse (SYMCLK) is generated

each n-bits, where n is defined by means of bits B2 to B0.

This pulse is used to update the register DMD3. Moreover,

it can be used as interrupt to the processor through the

IRQ1.3 (symbol interrupt).

The interrupt informs the controller that n bits are available

in the register DMD3.

The worst case time required to synchronize to incoming

data, when completely out of phase, is plotted for the

different baud rates in the following figure (see Fig.27).

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