PCA5010 datasheet(43/112 Pages) PHILIPS

43 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

SFR:

• TFREQ0 to TFREQ7: 8-bit register containing the

divisor of the tone. Loaded by the processor.

• ENB: enable frequency generator. Control signal from

processor.

• CLK2: use secondary clock input for tone generation.

If set a 32768 Hz clock signal is generated from the

primary 76800 Hz clock signal and used as a timing

reference for the tone generator.

Inputs:

• 76.8 kHz: Input to the tone counter.

Outputs:

• AT Output for alerter. Is logic 0 when disabled:

6.15.3

GENERATION OF THE 32768 HZ REFERENCE

The 32768 Hz reference is generated from 76800 Hz

according to the following algorithm:

forever do

begin

for 10 times do {

from 7 clocks on 76.8 kHz generate

3 pulses on 32 kHz

}

from 5 clocks on 76.8 kHz generate

2 pulses on 32 kHz

end

76.8 kHz

TFREQ

-----------------------

6.16

Watchdog timer

6.16.1

FUNCTION

The watchdog timer consists of an 8-bit down counter.

The binary number defined with WD3 to WD0 defines the

expiration time of the watchdog timer between 1 to 16 s.

Once enabled this counter is running continuously. Once

expired the timer produces firstly an interrupt and finally a

reset. The software must reload the watchdog in regular

intervals to avoid expiration.

A positive edge on the LD SFR bit (re)loads the counter

with the value of WD3 to WD0, sets the LOW bits to logic 1

and activates this counter if it is not yet running. However,

to prepare the (re)loading a positive edge must be applied

to the COND bit in WDCON. In this way at least two

locations in software must be passed before the counter

can be reloaded.

After reset the counter is not running. Only after the first LD

it is clocked continuously by a clock pulse of 16 Hz until the

DC/DC converter is switched off or an external reset is

applied.

If the next LD signal is not given within the defined expiry

interval an overflow occurs and the processor will be reset

(signal WDR). 1 clock cycle before the reset is applied an

WDI interrupt is issued. This gives the opportunity to avoid

the reset if required. The maximum watchdog expiry time

is thus 254

× 16 Hz ticks to the WD interrupt and

255

× 16 Hz ticks to the reset. If the DC/DC converter is in

the off mode, the watchdog timer is suspended.

6.16.2

WATCH DOG TIMER CONTROL REGISTER (WDCON)

The WDCON special function register is used to control the operation of the on-chip watchdog timer.

Table 34 Watchdog Control Register (WDCON, SFR address A5H)

Table 35 Description of the WDCON bits

76543210

COND

WD3

WD2

WD1

WD0

−−

BIT

SYMBOL

FUNCTION

WDCON.7

COND

Load condition. Control signal from processor.

WDCON.6

WD3

WD0 to WD3 is the preset value for the high nibble of the watchdog timer. The value is

the number of seconds to expiry of the watchdog.

WDCON.5

WD2

WDCON.4

WD1

WDCON.3

WD0

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