PCA5010 datasheet(32/112 Pages) PHILIPS

32 / 112 page

1998 Nov 02

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5010

6.11.2

CLOCK CORRECTION CONTROL REGISTER (CCON)

The CCON special function register is used to control the clock correction by software.

Table 20 Clock Correction Control Register (CCON, SFR address FCH)

Table 21 Description of the CCON bits

6.11.3

CLOCK CORRECTION INTERVAL REGISTERS (CC0 AND CC1)

The CC0 and CC1 special function registers (together with CCON.3 and CCON.4) are used to define the interval between

subsequent clock correction actions.

Table 22 Clock Correction Interval Register (CC0, SFR address FDH)

Table 23 Clock Correction Interval Register (CC1, SFR address FEH)

76543210

ENB

PLUS

TEST

CIV17

CIV16

−

BYPASS

SET

BIT

SYMBOL

FUNCTION

CCON.7

ENB

Enable clock correction. If ENB = 1 has been set, then correction is enabled and will

stay enabled even when the DC/DC converter is shut down and restarted.

CCON.6

PLUS

± Sign for value. If PLUS = 1 then clock pulses are inserted, or else deleted.

CCON.5

TEST

Test signal, must always be logic 0 in normal mode. It is used during test to bypass the

ﬁrst 9 FFs in the timing generator divider chain. If TEST = 1 the clock rate of the signals

9600 Hz and 256 Hz is doubled and the frequency on 16 Hz and 4 Hz is multiplied

by 300.

CCON.4

CIV17

bit 17 of interval value, is used as extension of CC0 and CC1

CCON.3

CIV16

bit 16 of interval value, is used as extension of CC0 and CC1

CCON.2

−

unused.

CCON.1

BYPASS

Test signal, must always be logic 0 in normal mode. It is used during test to generate

76.8 kHz on all outputs of the timing generator (4 Hz, 16 Hz, 256 Hz and 9600 Hz).

CCON.0

SET

A load signal to the interval register. After a logic 0 to logic 1 transition of this bit the

value of ENB, PLUS, TEST, BYPASS and CIV are copied into the local latches with the

next 76.8 kHz clock pulse. A duration of one MOV instruction is long enough for the set

operation to complete. The SFR values must remain stable for at least one oscillator

period because the actual transfer happens synchronized with the local clock

(see Figs 16 and 18).

76543210

CIV7

CIV6

CIV5

CIV4

CIV3

CIV2

CIV1

CIV0

76543210

CIV15

CIV14

CIV13

CIV12

CIV11

CIV10

CIV9

CIV8

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