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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STE100A датащи(PDF) 50 Page - STMicroelectronics |
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STE100A датащи(HTML) 50 Page - STMicroelectronics |
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50 / 82 page  Registers and descriptors description STE10/100A 50/82 0024h CRC16 of pattern 2 Reserved Wake-up pattern 2 offset 0028h Wake-up pattern 3 mask bits 31:0 002ch Wake-up pattern 3 mask bits 63:32 0030h Wake-up pattern 3 mask bits 95:64 0034h Wake-up pattern 3 mask bits 127:96 0038h CRC16 of pattern 3 Reserved Wake-up pattern 3 offset 003ch Wake-up pattern 4 mask bits 31:0 0040h Wake-up pattern 4 mask bits 63:32 0044h Wake-up pattern 4 mask bits 95:64 0048h Wake-up pattern 4 mask bits 127:96 004ch CRC16 of pattern 4 Reserved Wake-up pattern 4 offset 0050h Wake-up pattern 5 mask bits 31:0 0054h Wake-up pattern 5 mask bits 63:32 0058h Wake-up pattern 5 mask bits 95:64 005ch Wake-up pattern 5 mask bits 127:96 0060h CRC16 of pattern 5 Reserved Wake-up pattern 5 offset Offset value is from 0-255 (8-bit width). To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done. CSR15 (offset = 78h), WTMR - Watchdog timer 31~6 --- Reserved 5RWR Receive watchdog release. The time (in bit- times) from sensing dropped carrier to releasing watchdog timer. 0: 24 bit-times 1: 48 bit-times 4RWD Receive watchdog disable 0: If the received packet‘s length exceeds 2560 bytes, the watchdog timer will expire. 1: disable the receive watchdog. 3 --- Reserved Table 8. Control/status register description (continued) Bit # Name Description Default RW type |
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