STE100A datasheet(48/82 Pages) STMICROELECTRONICS

48 / 82 page

Registers and descriptors description

STE10/100A

48/82

1SCLK

Serial EEPROM clock.

High/Low this bit to provide the clock signal for

EEPROM.

1R/W

0SCS

Serial EEPROM chip select.

1: selects the serial EEPROM chip.

1R/W

CSR11 (offset = 58h), TMR - General - Purpose timer

31~17

---

Reserved

COM

Continuous operation mode.

1: sets the general-purpose timer in continuous

operating mode.

0R/W

15~0

GTV

General-purpose timer value.

Sets the counter value. This is a count-down

counter with a cycle time of 204us.

0R/W

CSR13 (offset = 68h), WCSR – Wake-up control/status register

---

Reserved

CRCT

CRC-16 type

0: Initial contents = 0000h

1: Initial contents = FFFFh

0R/W

WP1E

Wake-up pattern one matched enable

R/W

WP2E

Wake-up pattern two matched enable

R/W

WP3E

Wake-up pattern three matched enable

R/W

WP4E

Wake-up pattern four matched enable

R/W

WP5E

Wake-up pattern five matched enable

R/W

24-18

---

Reserved

LinkOFF

Link off detect enable. The STE10/100A will set

the LSC bit of CSR13 after it has detected that

link status has switched from ON to OFF.

0R/W

LinkON

Link on detect enable. The STE10/100A will set

the LSC bit of CSR13 after it has detected that

link status has switched from OFF to ON.

0R/W

15-11

---

Reserved

WFRE

Wake-up frame received enable. The

STE10/100A will include the “Wake-up Frame

Received” event in its set of wake-up events. If

this bit is set, STE10/100A will assert PMEST bit

of PMR1 (CR49) after STE10/100A has received

a matched wake-up frame.

0R/W

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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