STE100A datasheet(45/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

45/82

Force collision mode

0: disable

1: generate collision upon transmit (for testing in

loop-back mode)

0R/W**

11, 10

Operating mode

00: normal

01: MAC loop-back, regardless of contents of

XLBEN (bit 14 of XR0, XCVR loop-back)

10,11: reserved

R/W**

9, 8

---

Reserved

7MM

Multicast mode

1: receive all multicast packets

0R/W***

6PR

Promiscuous mode

1: receive any good packet.

0: receive only the right destination address

packets

1R/W***

SBC

Stop back-off counter

1: back-off counter stops when carrier is active,

and resumes when carrier is dropped.

0: back-off counter is not effected by carrier

0R/W**

---

Reserved

3PB

Pass bad packet

1: receives any packets passing address filter,

including runt packets, CRC error, truncated

packets. For receiving all bad packets, PR (bit 6

of CSR6) should be set to 1.

0: filters all bad packets

0R/W***

---

Reserved

1SR

Start/stop receive

0: receive processor will enter stop state after

the current frame reception is completed. This

value is effective only when the receive

processor is in the running or suspending state.

Note: In “Stop Receive” state, the PAUSE packet

and remote wake up packet will not be affected

and can be received if the corresponding

function is enabled.

1: receive processor will enter running state.

0R/W

---

Reserved

W* = only write when the transmit processor stopped.

W** = only write when the transmit and receive processor both stopped.

W*** = only write when the receive processor stopped.

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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