STE100A datasheet(47/82 Pages) STMICROELECTRONICS

47 / 82 page

STE10/100A

Registers and descriptors description

47/82

TDUIE

Transmit descriptor unavailable interrupt enable.

1: this bit in conjunction with NIE (bit 16 of

CSR7) will enable the transmit descriptor

unavailable interrupt.

0R/W

TPSIE

Transmit processor stopped interrupt enable.

1: this bit in conjunction with AIE (bit 15 of

CSR7) will enable the transmit processor

stopped interrupt.

0R/W

0TCIE

Transmit completed interrupt enable.

1: this bit in conjunction with NIE (bit 16 of

CSR7) will enable the transmit completed

interrupt.

0R/W

CSR8 (offset = 40h), LPC - Lost packet counter

31~17

---

Reserved

LPCO

Lost packet counter overflow.

1: when lost packet counter overflow occurs.

Cleared after read.

0RO/LH

15~0

LPC

Lost packet counter.

The counter is incremented whenever a packet

is discarded as a result of no host receive

descriptors being available. Cleared after read.

0RO/LH

CSR9 (offset = 48h), SPR - Serial port register

31~15

---

Reserved

SRC

Serial EEPROM read control.

When set, enables read access from EEPROM,

when SRS (CSR9 bit 11) is also set.

0R/W

SWC

Serial EEPROM write control.

When set, enables write access to EEPROM,

when SRS (CSR9 bit 11) is also set.

0R/W

---

Reserved

SRS

Serial EEPROM select.

When set, enables access to the serial

EEPROM (see description of CSR9 bit 14 and

CSR9 bit 13).

0R/W

10~4

---

Reserved

3SDO

Serial EEPROM data out.

This bit serially shifts data from the EEPROM to

the STE10/100A.

1RO

2SDI

Serial EEPROM data in.

This bit serially shifts data from the STE10/100A

to the EEPROM.

1R/W

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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