STE100A datasheet(36/82 Pages) STMICROELECTRONICS

36 / 82 page

Registers and descriptors description

STE10/100A

36/82

31~16

DID

Device ID, the device ID number of the STE10/100A

2774h

15~0

VID

Vendor ID, the vendor ID number of

STMicroelectronics

104Ah

CR48 (offset = c0h), PMR0, Power management register 0

PSD3c,

PSD3h,

PSD2,

PSD1,

PSD0

PME_Support.

The STE10/100A will assert PME# signal while in

the D0, D1, D2, D3hot and D3cold power state. The

STE10/100A supports Wake-up from the above five

states. Bit 31 (support wake-up from D3cold) is

loaded from EEPROM after power-up or hardware

reset. To support the D3cold wake-up function, an

auxiliary power source will be sensed during reset

by the STE10/100A Vaux_detect pin. If sensed low,

PSD3c will be set to 0; if sensed high, and if D3CS

(bit 31of CSR18) is set (CSR18 bits 16~31 are

recalled from EEPROM at reset), then bit 31 will be

set to 1.

X1111b

D2S

D2_Support. The STE10/100A supports the D2

Power management state.

1RO

D1S

D1_Support. The STE10/100A supports the D1

Power management state.

1RO

24~22

AUXC

Aux current. These three bits report the maximum

3.3Vaux current requirements for STE10/100A chip.

If bit 31 of PMR0 is ‘1’, the default value is 111b,

meaning the STE10/100A needs 375 mA to support

remote wake-up in D3cold power state. Otherwise,

the default value is 000b, meaning the STE10/100A

does not support remote wake-up from D3cold

power state.

XXXb

DSI

The device specific initialization bit indicates

whether any special initialization of this function is

required before the generic class device driver is

able to use it.

0: indicates that the function does not require a

device-specific initialization sequence following

transition to the D0 uninitialized state.

0RO

---

Reserved

PMEC

PME Clock. Indicates that the STE10/100A does not

rely on the presence of the PCI clock for PME#

operation.

0RO

18~16

VER

Version. The value of 010b indicates that the

STE10/100A complies with revision 1.0a of the PCI

power management interface specification.

010b

15~8

NIP

Next item pointer. This value is always 0h, indicating

that there are no additional items in the capabilities

list.

00h

Table 6.

Configuration registers description (continued)

Bit #

Name

Description

Default

RW type

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