STE100A datasheet(64/82 Pages) STMICROELECTRONICS

64 / 82 page

Registers and descriptors description

STE10/100A

64/82

0REF

Receive error full interrupt.

0: the receive error number is less than 64.

1: 64 error packets is received.

0RO/LH*

LH = High Latching and cleared by reading.

XR9(offset = d8h) - XIE, XCVR interrupt enable register

15~7

---

Reserved

ANCE

Auto-negotiation completed interrupt enable.

0: disable auto-negotiation completed interrupt.

1: enable auto-negotiation complete interrupt.

0R/W

5RFE

Remote fault detected interrupt enable.

0: disable remote fault detection interrupt.

1: enable remote fault detection interrupt.

0R/W

4LDE

Link down interrupt enable.

0: disable link fail interrupt.

1: enable link fail interrupt.

0R/W

3ANAE

Auto-negotiation acknowledge interrupt enable.

0: disable link partner acknowledge interrupt

1: enable link partner acknowledge interrupt.

0R/W

2PDFE

Parallel detection fault interrupt enable.

0: disable fault parallel detection interrupt.

1: enable fault parallel detection interrupt.

0R/W

1ANPE

Auto-negotiation page received interrupt enable.

0: disable auto-negotiation page received

interrupt.

1: enable auto-negotiation page received

interrupt.

0R/W

0REFE

RX_ERR full interrupt enable.

0: disable rx_err full interrupt.

1: enable rx_err interrupt.

0R/W

XR10(offset = dch) - 100CTR, 100BASE-TX control register

15,14

---

Reserved

DISRER

Disable the RX_ERR counter.

0: the receive error counter - RX_ERR is

enabled.

1: the receive error counter - RX_ERR is

disabled.

0R/W

ANC

Auto-negotiation completed. This bit is the same

as bit 5 of XR1.

0: the auto-negotiation process has not

completed yet.

1: the auto-negotiation process has completed.

0RO

Table 10.

Transceiver registers description (continued)

Bit #

Name

Description

Default

RW type

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