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STE100A датащи(PDF) 69 Page - STMicroelectronics

номер детали STE100A
подробное описание детали  PCI 10/100 Ethernet controller with integrated PHY (3.3V)
PDF  82 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE100A датащи(HTML) 69 Page - STMicroelectronics

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STE10/100A
Registers and descriptors description
69/82
29
FS
First descriptor
28,27
---
Reserved
26
AC
Disable add CRC function
25
TER
End of ring
24
TCH
2nd address chain. Indicates that the buffer 2 address is the next descriptor
address
23
DPD
Disable padding function
22
---
Reserved
21-11
TBS2
Buffer 2 size
10-0
TBS1
Buffer 1 size
TDES2
31~0
BA1
Buffer address 1. No alignment limitations imposed on the transmission
buffer address.
TDES3
31~0
BA2
Buffer address 2. No alignment limitations imposed on the transmission
buffer address.
Table 14.
Transmit descriptor description (continued)
Bit#
Name
Description



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