STE100A datasheet(40/82 Pages) STMICROELECTRONICS

40 / 82 page

Registers and descriptors description

STE10/100A

40/82

Table 8.

Control/status register description

Bit #

Name

Description

Default

RW type

CSR0 (offset = 00h), PAR - PCI access register

31~25

---

Reserved

MWIE

Memory write and invalidate enable.

1: enable STE10/100A to generate memory

write invalidate command. The STE10/100A will

generate this command while writing full cache

lines.

0: disable generating memory write invalidate

command. The STE10/100A will use memory

write commands instead.

0R/W*

MRLE

Memory read line enable.

1: enable STE10/100A to generate memory read

line command when read access instruction

reaches the cache line boundary. If the read

access instruction doesn’t reach the cache line

boundary then the STE10/100A uses the

memory read command instead.

0R/W*

---

Reserved

MRME

Memory read multiple enable.

1: enable STE10/100A to generate memory read

multiple commands when reading a full cache

line. If the memory is not cache-aligned, the

STE10/100A uses the memory read command

instead.

0R/W*

20~19

---

Reserved

18,17

TAP

Transmit auto-polling in transmit suspended

state.

00: disable auto-polling (default)

01: polling own-bit every 200 us

10: polling own-bit every 800 us

11: polling own-bit every 1600 us

R/W*

---

Reserved

15, 14

CAL

Cache alignment. Address boundary for data

burst, set after reset

00: reserved (default)

01: 8 DW boundary alignment

10: 16 DW boundary alignment

11: 32 DW boundary alignment

R/W*

13 ~ 8

PBL

Programmable burst length. This value defines

the maximum number of DW to be transferred in

one DMA transaction.

Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32

000000

R/W*

STE100A датащи(PDF) 40 Page - STMicroelectronics

STE100A датащи(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

датащи скачать

ссылки URL