STE100A datasheet(53/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

53/82

ANISE

Added normal interrupt summary enable.

1: adds the interrupts of bits 30 and 31 of

ACSR7 (CSR17) to the normal interrupt

summary (bit 16 of CSR5).

0R/W

AAIE

Added abnormal interrupt summary enable.

1: adds the interrupt of bits 27, 28, and 29 of

ACSR7 (CSR17) to the abnormal interrupt

summary (bit 16 of CSR5).

0R/W

14~0

These bits are the same as the interrupt enable

either CSR7 or CSR16.

CSR18 (offset = 88h), CR - Command register bit31 to bit16 automatically recall from EEPROM

D3CS

D3cold power state wake up support. If this bit is

reset then bit 31 of PMR0 will be reset to ‘0’. If

this bit is asserted and an auxiliary power source

is detected then bit 31 of PMR0 will be set to ‘1’.

from

EEPROM

R/W

30-28

AUXCL

Aux. current load. These three bits report the

maximum 3.3Vaux current requirements for

STE10/100A chip. If bit 31 of PMR0 is ‘1’, the

default value is 111b, which means the

STE10/100A need 375 mA to support remote

wake-up in D3cold power state. Otherwise, the

default value is 000b, which means the

STE10/100A does not support remote wake-up

from D3cold power state.

000b

from

EEPROM

R/W

27-24

---

Reserved

4LEDmod

e_on

This bit is used to control the LED mode

selection.

If this bit is reset, mode 1 (3 LEDs) is selected;

the LEDs definition is:

- 100/10 speed

- Link/activity

- Full duplex/collision

If this bit is set, mode 2 (4 LEDs) is selected; the

LEDs definition is:

- 100 link

- 10 link

- Activity

- Full duplex/collision

from

EEPROM

R/W

22, 21

RFS

Receive FIFO size control

11: 1K bytes

10: 2K bytes

01,00: reserved

from

EEPROM

R/W

---

Reserved

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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