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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STE100A датащи(PDF) 74 Page - STMicroelectronics |
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STE100A датащи(HTML) 74 Page - STMicroelectronics |
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74 / 82 page  Electrical specifications and timings STE10/100A 74/82 Figure 16. PCI clock waveform Table 21. X1 specifications Symbol Parameter Test condition Min. Typ. Max. Units TX1d X1 duty cycle 45 50 55 % TX1p X1 period 30 ns TX1t X1 tolerance + / - 50 PPM TX1CL X1 load capacitance 18 pF Table 22. PCI timing Symbol Parameter Test condition Min. Typ. Max. Units Tval Clock to signal valid delay (bussed signals) 211 ns Tval(ptp) Clock to signal valid delay (point to point) 211 ns Ton Float to active delay 2 ns Toff Active to float delay 28 ns Tsu Input set up time to clock (bussed signals) 7ns Tsu(ptp) Input set up time to clock (point to point) 10,12 ns Th Input hold time from clock 0 ns Th Input hold time from clock 0 ns Trst Reset active time after power stable 1ms Trst-clk Reset active time after clk stable 100 µs Trst-off Reset active to output float delay 40 ns 0.475Vcc 0.4Vcc 0.2Vcc 0.325Vcc Th Tl Tc 0.4Vcc, p-to-p minimum 0.6Vcc |
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