STE100A datasheet(33/82 Pages) STMICROELECTRONICS

33 / 82 page

STE10/100A

Registers and descriptors description

33/82

New capabilities. Indicates whether the STE10/100A

provides a list of extended capabilities, such as PCI

power management.

1: the STE10/100A provides the PCI management

function.

0: the STE10/100A doesn’t provide new capabilities.

Same as

bit 19 of

CSR18

19~ 9

---

Reserved

8CSE

Command system error response.

1: enable system error response. The STE10/100A

will assert SERR# when it finds a parity error during

the address phase.

1R/W

---

Reserved

6CPE

Command parity error response.

0: disable parity error response. STE10/100A will

ignore any detected parity error and keep on

operating. Default value is 0.

1: enable parity error response. STE10/100A will

assert system error (bit 13 of CSR5) when a parity

error is detected.

0R/W

5~ 3

---

Reserved

2CMO

Command master operation ability.

0: disable the STE10/100A bus master ability.

1: enable the PCI bus master ability. Default value is

1 for normal operation.

1R/W

CMSA

Command memory space access.

0: disable the memory space access ability.

1: enable the memory space access ability.

1R/W

0CIOSA

Command I/O space access.

0: enable the I/O space access ability.

1: disable the I/O space access ability.

1R/W

R/W: Read and write able. RO: Read able only.

CR2 (offset = 08h), CC - Class code and revision number

31~24

BCC

Base class code. It means STE10/100A is a network

controller.

02h

23~16

Subclass code. It means STE10/100A is a fast

ethernet controller.

00h

15~ 8

---

Reserved

7 ~ 4

Revision number, identifies the revision number of

STE10/100A

3 ~ 0

Step number, identifies the STE10/100A steps

within the current revision

RO: Read only

Table 6.

Configuration registers description (continued)

Bit #

Name

Description

Default

RW type

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