ADF4377 datasheet(25/79 Pages) AD

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Data Sheet

ADF4377

THEORY OF OPERATION

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Rev. 0 | 25 of 79

Figure 66. Bleed Current Delay Step Size

Bleed current delay (tIDEL) is determined by tIDEL-STEP, the

BLEED_POL bit, and BLEED_I bit fields, Bits[9:0]. Refer to Equa-

tion 10 and Equation 11.

If BLEED_POL = 0, the propagation delay from the REFP and

REFN input pins to the CLKxP and CLKxN output pins increases.

Refer to Figure 19.

tIDEL=tIDEL−STEP×BLD_I

(10)

where BLD_I represents the decimal value of the BLEED_I bit field,

Bits[9:0].

If BLEED_POL = 1, the propagation delay from the REFP and

REFN input pins to the CLKxP and CLKxN output pins decreases.

Refer to Figure 22

tIDEL=−tIDEL−STEP×BLD_I

(11)

The maximum tIDEL for proper lock detector functionality is based

on the LDWIN_PW setting, as shown in Table 16.

INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and BLEED_POL can

be used in conjunction to align the multichip output to output skew

to as small as ±0.05 ps (see Equation 9). The largest BLEED_I

bit fields, Bits[9:0] settings may increase LNORM by 1 dB and L1/f

by 4 dB, as shown in Figure 36. INV_CLKOUT does not degrade

performance and must be used to adjust for multichip output to

output skews greater than a quarter of the 1/fOUT period, in lieu

of a large BLEED_I bit fields, Bits[9:0] value. As a result, the

maximum tIDEL adjustment never needs to be more than a quarter

of the 1/fOUT period. See the Applications Information section for the

relationship between R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit

fields, Bits[9:0], and BLEED_POL.

Lock Detector

The lock detector uses internal signals from the PFD to measure

phase coincidence between the output signal of the reference

divider and doubler (RCLK) in Figure 62 and the output signal of

the feedback divider (NCLK) in Figure 72. It is enabled by setting

both the EN_LOL bit and the EN_LDWIN bit to 1 and presents the

lock detector output on the LKDET pin and the LOCKED bit. The

lock detector output can also be presented on the MUXOUT pin by

programming the MUXOUT bits (see Figure 75). The CMOS_OV bit

determines if the logic high level for the MUXOUT, LKDET, SDO,

and SDIO output pins is 3.3 V or 1.8 V.

The PFD phase difference must be less than the phase difference

lock window time (tLDWIN) for a set number of PFD cycles before the

lock detector output indicates that the PLL has locked. The desired

number of PFD cycles varies if a designer prioritizes lock detect

accuracy or speed. Five loop filter time constants can be used as

an initial estimate of the desired number of PFD cycles, as shown

in Equation 12. The desired number of PFD cycles is set by the

LD_COUNT bits, as shown in Table 14. Refer to Figure 67 and

Table 15 for more details.

PFD Cycles= 5×fPFD

2×π×LPBW

(12)

where LPBW = loop filter bandwidth.

Table 14. LD_COUNT Programming

LD_COUNT

PFD Cycles

134

191

270

383

542

767

1085

1535

2171

3071

4343

6143

8687

12287

17376

24575

34754

49151

69510

98303

139021

196607

278044

393215

556090

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