ADF4377 datasheet(43/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 43 of 79

noise floor of the output, which then impacts the in-band perform-

ance of the ADF4377. As a result, the Stage 1 reference and

SYSREF distribution IC ∆t blocks are recommended for SYSREF

signals only.

Skew Measurement, Adjustments and System

Error

In Figure 92, a TDC is shown in the AD9213. The AD9213 TDC has

the ability to measure the time delta between the rising edge of the

AD9213 SYSREF input (tSYSREF) and the rising edge of the AD9213

clock input (tCLK) as shown in Equation 26.

∆tCLK_SYSREF=tCLK−tSYSREF

(26)

To determine the clock skew between the clock inputs of the

first AD9213 device and the second AD9213 device, measure the

∆tCLK_SYSREF for both AD9213 devices.

∆tCLK_SYSREFA=tCLKA−tSYSREFA

∆tCLK_SYSREFB=tCLKB−tSYSREFB

By making the assumption that the SYSREFA and SYSREFB

signals arrive at both AD9213 devices at the same moment in time,

the clock to clock skew between both AD9213 devices can be

calculated as shown in the following equation.

Assume, tSYSREFA − tERROR = tSYSREFB

tCLK_SKEW=∆tCLK_SYSREFA−∆tCLK_SYSREFB

tCLK_SKEW= tCLKA−tSYSREFA − tCLKB−tSYSREFB

substituting, tSYSREFA−tERROR for tSYSREFB

tCLK_SKEW=tCLKA−tCLKB+tERROR

If care is taken in the Board Layout Considerations section, tERROR

limits the clock skew accuracy to roughly 5 ps to 10 ps. This error is

due to the sum of errors from the SYSREF output skew from Stage

1, SYSREFA, and SYSREFB electrical trace matching, and the first

AD9213 and the second AD9213 TDC measurement error. Contact

ADI if less than 5 ps to 10 ps clock skew accuracy at the clock

inputs of the AD9213 is required.

After tCLK_SKEW is calculated, program the second ADF4377 skew

adjustment using Method 2, as shown in Figure 91. After the

skew adjustment is programmed, a tCLK_SKEW measurement can

be repeated as necessary to further fine tune the adjustment or

average out measurement repeatability error.

Power-Up, Programming, and Measurement

Sequence

The following list provides the recommended system level power-

up, device programming, and skew measurement sequence:

1. Power up system

2. Program Stage 1 IC, ADF4377 devices, and AD9213 devices to

their expected frequency plan

3. Allow temperature of the components to settle

4. Perform clock skew measurement

5. Program skew adjustments per Method 2, as shown in Figure

6. Perform JESD204B/C initialization

ADC CLOCK AND JITTER CONSIDERATIONS

Estimating ADC SNR and Clock Jitter

Requirements

Adding noise directly to a clean signal reduces its signal-to-noise

ratio (SNR). In data acquisition applications, digitizing a clean signal

with a noisy clock signal also degrades the SNR. This issue is

best explained in the time domain by using jitter instead of phase

noise. For this discussion, assume that the jitter is white (flat with

frequency) and of Gaussian distribution.

Figure 93 shows a sine wave signal entering a typical data acquisi-

tion circuit composed of an ADC, an input signal amplifier, and a

sampling clock. Also shown in Figure 93 are three signal sampling

scenarios for sampling the sine wave at its zero crossing.

In the first scenario, a perfect sine wave input is buffered by a

noiseless amplifier to drive the ADC. Sampling is performed by

a perfect, zero jitter clock. Without any added noise or sampling

clock jitter, the digitized output value of the ADC is very clearly

determined and perfectly repeatable from cycle to cycle.

In the second scenario, a perfect sine wave input is buffered by

a noisy amplifier to drive the ADC. Sampling is performed by a

perfect, zero jitter clock. The added noise results in an uncertainty

in the digitized value, causing an error term that degrades the SNR.

The degraded SNR in this scenario, from adding noise to the signal,

is expected.

In the third scenario, a perfect sine wave input is buffered by a

noiseless amplifier to drive the ADC. Sampling is performed by a

clock signal with added jitter. Note that as the signal is slewing, the

jitter of the clock signal leads to an uncertainty in the digitized value

and an error term, like in the second scenario. Again, this error term

degrades the SNR.

A real-world system has both additive amplifier noise and sample

clock jitter. After the signal is digitized, determining the root cause

of any SNR degradation, amplifier noise or sampling clock jitter, is

essentially impossible.

Figure 93. A Typical Data Acquisition Circuit Showing the Sampling Error

Effects of a Noisy Amplifier and a Jittery Clock

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