ADF4377 datasheet(35/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 35 of 79

DESIGN AND PROGRAMMING EXAMPLE 1:

SINGLE ADF4377

A single ADF4377 clocks a single ADC. The purpose of this exam-

ple is to provide a method to determine the correct inputs required

to design a loop filter in ADIsimPLL, provide a method to manually

generate all ADF4377 register settings, and provide the method to

perform a VCO autocalibration on initial power-up and bypass or

override the VCO autocalibration on all future device power-ups.

In practice, the ADF4377 evaluation board graphical user interface

(GUI) register automates the register generation process and can

replace and/or verify the manual register generation method.

For this design example, assume the following design goals:

►

Reference input, 125 MHz, single-ended 7 dBm sine wave, 50 Ω

environment

►

Output of 12 GHz

►

SPI requirements of 1.8 V, 4 wire SPI, optimize SPI write se-

quence

►

Prioritize designing for the lowest jitter performance over other

design criteria

Design Procedure

The following design procedure aids in schematic design and SPI

1. Select the settings for reference and loop filter design (see the

Reference and Loop Filter Design section)

2. Select the output, frequency, and amplitude (see the Output

Selection, Frequency and Amplitude section)

3. Select the settings for the reference to output propagation

delay (see the Reference to Output Propagation Delay Settings

section)

4. Select the lock detector settings (see the Lock Detector Set-

tings section)

5. Select the VCO automatic calibration settings (see the VCO

Automatic Calibration Settings section)

6. Select the double buffer and manual VCO calibration settings

(see the Double Buffer and Manual VCO Calibration Settings

section)

7. Select the SPI protocol settings (see the SPI Protocol Settings

section)

8. Select the remaining register settings (see the Remaining Reg-

ister Settings section)

Reference and Loop Filter Design

To design a loop filter in ADIsimPLL, the user must determine the

desired reference input settings, charge pump settings, and PFD

frequency. The design goals provided in the Design and Program-

ming Example 1: Single ADF4377 section state to prioritize the

lowest jitter performance over other design criteria. To design the

lowest jitter loop filter, determine the register settings that minimize

the output phase noise characteristics as described in the Output

Phase Noise Characteristics section.

The In-Band Output Phase Noise section states the maximum fPFD

minimizes LOUT. The maximum fPFD is obtained with the reference

doubler enabled and the reference divider bypassed (see the Refer-

ence Divider (R) and Doubler (D) section). To enable the reference

doubler, set EN_RDBLR = 1. The reference divider is bypassed and

can remain at its power on reset state (R_DIV = 1). Solve Equation

7 for the maximum fPFD.

fPFD=D×fREF=2×125 MHz=250 MHz

The Charge Pump section states that larger ICP results in lower

LNORM, as shown in Figure 40. Set CP_I = 15 to minimize LNORM.

Selecting the optimal reference input buffer amplifier (see the Ref-

erence Input Buffer section) based on the reference input slew

rate also minimizes LNORM (see Figure 37). Solve Equation 23 and

Equation 8 for the reference input slew rate.

VPK= 2× 10 PdBm/10×50 Ω/1000 mW (23)

VPK= 2× 10 7 dBm/10×50 Ω/1000 mW =0.707

VPKSlew Rate =2×π×fREF×VPK=2×π×125

MHz×0.707=556 V/υs

Based on Table 7 and Figure 37, a reference input slew rate of 556

V/μs minimizes LNORM when the LNA reference amplifier is selected

by setting REF_SEL = 1. When the LNA reference amplifier is

selected, Table 8 requires FILT_REF = 0 when fREF = 125 MHz, and

Table 9 requires BST_REF = 1 when VREF = 2 × 0.707 VPK = 1.414

V p-p.

The reference peak detector (see the Reference Peak Detector

section) consumes minimal power, ~10 mW, and does not degrade

performance. As a result, PD_RDET can be set to 0 or 1 to meet

the design goals. The reference and loop filter design was created

with PD_RDET = 0 to allow for the option to monitor the reference

signal with the REF_OK bit.

Table 25. SPI Summary, Reference and Loop Filter Design

Bit Field

Value

EN_RDBLR

0x1

R_DIV

0x1

CP_I

0xF

REF_SEL

0x1

FILT_REF

0x0

BST_REF

0x1

PD_RDET

0x0

For the recommended reference input network, refer to Figure 80,

single-ended 50 Ω source (VREFIN < 2.6 V p-p).

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