ADF4377 datasheet(36/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 36 of 79

For ADIsimPLL loop filter design, note that the selected LNA refer-

ence amplifier has a higher gain than the DMA reference amplifier.

As a result, the LNA generates larger reference spurious content,

which requires a 5th order loop filter design to achieve the stated

typical spurious performance of −100 dBc. However, the DMA has

less reference spurious content and can use a simpler 4th order

loop filter design for the same spurious result. For the purposes of

the reference and loop filter design, assume ADIsimPLL created a

loop filter with a 460 kHz loop bandwidth. The loop filter bandwidth

is used to determine the LD_COUNT setting in the Lock Detector

Settings section.

Output Selection, Frequency and Amplitude

The Design and Programming Example 1: Single ADF4377 section

design goals require fOUT = 12 GHz. Table 18 sets CLKOUT_DIV

= 0 and O = 1 when fOUT = 12 GHz. The PLL feedback divider

bit fields, N_INT, Bits[11:0], can be determined from Equation 4,

Equation 6, and Table 20.

fOUT=fVCO

/O=fVCO

fVCO

=fREF×D×N×O, solving for N produces

=fVCO/fREF×D×O =12 GHz/125 MHz×2×1

48, N_INT setting

The clock output buffer amplitude (see the Clock Output Buffer

section) does not have a noticeable effect on jitter performance,

see Figure 9. However, Figure 47 indicates that lower amplitudes

decrease the supply current. Therefore, choose the lowest ampli-

tude setting the ADC clock input accepts. For the frequency and

amplitude output selection, choose the CLK1P and CLK1N clock

output buffer amplitude by setting CLKOUT1_OP = 1 (see Figure

30 and Table 21).

Enable the output of CLK1P and CLK1N by setting the ENCLK1 pin

to logic high and setting PD_CLKOUT1 = 0. Because this example

clocks a single ADC, the output of CLK2P and CLK2N is pow-

ered down. Power down CLK2P and CLK2N either by setting the

ENCLK2 pin to a logic low and/or setting the PD_CLKOUT2 bit = 1.

Because CLK2P and CLK2N is powered down, the CLKOUT2_OP

amplitude setting can remain at its power on reset state of 0.

Common ADF4377 clock output networks are shown in Figure 98.

Table 26. SPI Summary, Output Selection, Frequency and Amplitude

Bit Field

Value

CLKOUT_DIV

0x0

N_INT, Bits[11:0]

0x30

CKLOUT1_OP

0x1

CLKOUT2_OP

0x0

PD_CLKOUT1

0x0

PD_CLKOUT2

0x1

Reference to Output Propagation Delay

Settings

Reference to output propagation delay was not mentioned in the

Design and Programming Example 1: Single ADF4377 section. In

the Design and Programming Example 1: Single ADF4377 section,

it was stated to prioritize to the lowest jitter performance. Setting

the reference to output delay controls to their minimum setting

achieves the lowest jitter by minimizing LNORM and L1/f (see Figure

12, Figure 15, Figure 36, and Figure 39). As shown in Figure 14,

the INV_CLKOUT setting does not affect jitter performance and can

remain at its power on reset state of 0.

Table 27. SPI Summary, Propagation Delay

Bit Field

Value

EN_BLEED

0x0

BLEED_I bit fields, Bits[9:0]

0x0

BLEED_POL

0x0

R_DEL

0x0

N_DEL

0x0

INV_CLKOUT

0x0

Lock Detector Settings

To enable the lock detector (see the Lock Detector section), set

the EN_LOL and EN_LDWIN bits to 1. The LD_COUNT bit field

is determined by Equation 12. As mentioned in the Reference and

Loop Filter Design section, a 460 kHz loop bandwidth (LPBW) was

assumed.

PFD Cycles=fPFD×5/2×π×LPBW =250

MHz×5/2×π×460 kHz =432

The calculated minimum PFD cycle count of 432 is then compared

to the PFD cycle column in Table 14, which results in 542 PFD

cycles and LD_COUNT = 9.

To determine the LDWIN_PW setting from Table 16, calculate tIDEL

from Equation 10 or Equation 11. Because the BLEED_I bit fields,

Bits[9:0], is set to 0 in the Reference to Output Propagation Delay

Settings section, tIDEL = 0. Based on Table 16, when tIDEL = 0,

LDWIN_PW is set to 0. The RST_LD bit is related to the lock

detector and is set to 0 in normal use cases.

Table 28. SPI Summary, Lock Detector

Bit Field

Value

EN_LOL

0x1

EN_LDWIN

0x1

LD_COUNT

0x9

LDWIN_PW

0x0

RST_LD

0x0

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