ADF4377 datasheet(61/79 Pages) AD

61 / 79 page

Data Sheet

ADF4377

analog.com

Rev. 0 | 61 of 79

Figure 132.

Table 69. Bit Descriptions for REG001E

Bits

Bit Name

Description

Reset

Access

R01E_RSV6

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R01E_RSV5

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

[5:4]

R01E_RSV4

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R01E_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R01E_RSV2

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

[1:0]

R01E_RSV1

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x1F, Reset: 0x00, Name: REG001F

Figure 133.

Table 70. Bit Descriptions for REG001F

Bits

Bit Name

Description

Reset

Access

BST_REF

Enable LNA Reference Input Buffer Gain Boost for Low Amplitude Input. Refer to Table 9.

0x0

R/W

0: disabled.

1: enabled.

FILT_REF

Enable LNA Reference Input Buffer Filter. Refer to Table 8.

0x0

R/W

0: disabled.

1: enabled.

REF_SEL

Select the Reference Input Buffer. Refer to Table 7.

0x0

R/W

0: DMA for an improved reference input to clock output propagation delay temperature coefficient.

1: LNA for improved PLL in-band noise when a low slew rate signal is applied to the reference input.

R01F_RSV2

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

[3:0]

R01F_RSV1

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x20, Reset: 0x00, Name: REG0020

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