ADF4377 datasheet(30/79 Pages) AD

30 / 79 page

Data Sheet

ADF4377

THEORY OF OPERATION

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Rev. 0 | 30 of 79

Table 22. ADC Register Setup for SPI Clock and RCLK

Bits

RCLK1

SPI Clock

ADC_A_CONV, EN_AUTOCAL

Not applicable

EN_ADC_CNV, EN_ADC,

EN_ADC_CLK

PD_ADC

1 Required when writing to REG0010 to start the ADC conversion and VCO

calibration.

After the bits in Table 22 are programmed, start an ADC conver-

sion with either, a register write to REG0045 or a register write

to REG0010 (RCLK only). With a REG0010 write, a VCO calibra-

tion (see the VCO Calibration section) begins immediately after

the ADC conversion is complete. An ADC conversion requires

17 clock cycles to complete. In serial port register REG0049,

the ADC_BUSY bit monitors the conversion status. During a con-

version, ADC_BUSY is set to 1 and on conversion completion,

ADC_BUSY is set to 0.

Measurements are recorded in the CHIP_TEMP bit fields, Bits[8:0],

in REG004C and REG004D (see Figure 76).

If an ambient temperature measurement is desired, program the

ADF4377 to a low power state, as shown in Table 23. For ambient

temperature measurements, the SPI clock is the only available

clock option.

Table 23. Ambient Temperature Full Power Down Register Setup

Bit Fields

State

ADC_CLK_SEL

PD_ADC

PD_CLK, PD_RDET, PD_CALDAC, PD_NDIV,

PD_VCO, PD_LD, PD_PFDCP, PD_CLKOUT1,

PD_CLKOUT2, PD_RDIV

Double Buffering

Double buffering refers to a main/subordinate configuration for the

bit fields shown in Table 24. Only the subordinate bit fields control

the actual state of the ADF4377. When double buffering is enabled

for a bit field, the serial interface only writes to the main bit field.

The subordinate bit field retains its previous value until a register

write is sent to REG0010. After writing to REG0010, all main bit

fields are automatically loaded to their respective subordinate bit

field. Writing to REG0010 also starts the autocalibration of the VCO

(see the VCO Calibration section). This allows the user to update

several bit fields that change the output frequency of the ADF4377

and start a new VCO calibration on the same register write. When

double buffering is disabled, the serial interface writes directly to the

subordinate bit field.

It is possible to read back the state of either the main or

subordinate bit fields by enabling or disabling the MAIN_READ-

BACK_CONTROL bit.

Table 24. Double Buffer Enable Bits and Bit Fields

Double Buffer Enable Bits

Double Buffered Bit Fields

Not applicable, always enabled

N_INT bits, Bits[11:0], R_DIV,

EN_RDBLR, CP_I

CLKODIV_DB

CLKOUT_DIV

DCLK_DIV_DB

DCLK_DIV1, DCLK_DIV2

O_VCO_DB

M_VCO_CORE, M_VCO_BAND,

M_VCO_BIAS

DEL_CTRL_DB

INV_CLKOUT, BLEED_I bits, Bits[9:0],

BLEED_POL, N_DEL, R_DEL

Serial Port

The SPI-compatible serial port provides control and monitoring

functionality. The CMOS_OV bit determines if the logic high level

for the SDO and SDIO SPI output pins is 3.3 V or 1.8 V. CMOS_OV

also sets the output level for MUXOUT and LKDET.

The serial port can be programmed to support several different

configurations in REG0000 and REG0001.

The SDO_ACTIVE bit determines if the serial port is configured as

a 3-wire or 4-wire serial interface (see the timing diagrams in Figure

2, Figure 3, and Figure 4).

As shown in Figure 77 and Figure 78, the instruction cycle is

composed of 16 bits. The fifteen LSB bits determine the register

address, and the MSB determines if data is written to or read from

the serial interface during the data transfer cycle. The LSB_FIRST

bit determines the data orientation of the instruction cycle and data

transfer cycle of the serial interface.

Figure 77. Serial Interface, MSB First (LSB_FIRST = 0)

Figure 78. Serial Interface, LSB First (LSB_FIRST = 1)

The SPI register map can be programmed with single instructions,

as shown in Figure 77 and Figure 78, or in streaming mode,

as shown in Figure 79. Streaming mode allows for efficient data

transfer read or write cycles to multiple registers. Streaming mode

allows the user to program a bit stream composed of one register

address in the instruction header and data for that register address,

which is then followed by data in subsequent register addresses.

The ADDRESS_ASCENSION bit determines if the subsequent reg-

ister addresses are incremented or decremented. It is recommend-

ed to decrement the register addresses in streaming mode (AD-

DRESS_ASCENSION = 0). The reason for this recommendation is

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