ADF4377 datasheet(58/79 Pages) AD

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Data Sheet

ADF4377

analog.com

Rev. 0 | 58 of 79

Table 64. Bit Descriptions for REG0019

Bits

Bit Name

Description

Reset

Access

1: power-down.

PD_ADC

Power Down the Temperature ADC.

0x0

R/W

0: active. Normal operation.

1: power-down.

PD_CALDAC

Power Down the VCO Calibration Digital to Analog Converter (DAC).

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

Address: 0x1A, Reset: 0x83, Name: REG001A

Figure 128.

Table 65. Bit Descriptions for REG001A

Bits

Bit Name

Description

Reset

Access

PD_ALL

Main Power Down.

0x1

R/W

0: active.

1: power-down. Does not reset SPI registers to POR state. Refer to the Power-Up and Initialization Sequence

section.

PD_RDIV

Power Down the Reference Divider and Doubler.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_NDIV

Power Down the Feedback Divider.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_VCO

Power Down the VCO.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_LD

Power Down the Lock Detector.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_PFDCP

Power Down the PFD and CP.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_CLKOUT1

Power Down Clock Output Buffer to Pins CLK1N and CLK1P.

0x1

R/W

0: active. Normal operation.

1: power-down.

PD_CLKOUT2

Power Down Clock Output Buffer to Pins CLK2N and CLK2P.

0x1

R/W

0: active. Normal operation.

1: power-down.

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