ADF4377 datasheet(45/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 45 of 79

Assuming the inherent aperture jitter of the ADC (tJ(ADC)) is known,

the jitter of the clock generator (tJ(CLK)) is obtained using Equation

28.

ADC Sample Clock Input Drive Requirements

Modern high speed, high resolution ADCs have a high dynamic

range and are sensitive to any unwanted noise or spurious source.

Noise or interfering signals on the analog signal input, the voltage

reference, or the sampling clock input can easily appear in the

digitized data. To deliver the full performance of any ADC, the

sampling clock input must be driven with a clean, low jitter signal.

Figure 96 shows a simplified version of a typical ADC sample clock

input. In Figure 96, the input pins may be labeled ENC± for encode

or CLK± for clock in different ADCs. The input is composed of a

differential limiting amplifier stage followed by a buffer that directly

controls the track and hold stage of the ADC.

Figure 96. Simplified Sample Clock Input Circuit

The sample clock input amplifier also benefits from a fast slewing

input signal because the amplifier has noise of its own. By slewing

through the crossover region quickly, the amplifier noise creates

less jitter than if the transition were slow. As shown in Figure 96,

the sample clock input of the ADC is typically differential, with a dif-

ferential sampling clock delivering the best performance. Figure 96

also shows the sample clock input with a different common-mode

input voltage than the outputs of the ADF4377. Most ADC applica-

tions require ac coupling to convert between the two common-mode

voltages.

Transmission Lines and Termination

Interconnection of high speed signaling with fast rise and fall times

requires the use of transmission lines with properly matched termi-

nation. The transmission lines may be stripline, microstrip or any

other design topology. A detailed discussion of transmission line

design is beyond the scope of this data sheet. Any mismatch be-

tween the characteristic impedance of the transmission line and the

terminating impedance results in a portion of the signal reflecting

back toward the other end of the transmission line. In the extreme

case of an open or short-circuit termination, all of the signal is

reflected back. This signal reflection leads to overshoot and ringing

on the waveform. Figure 97 shows the preferred method of far-end

termination of the transmission line.

Figure 97. Far-End Transmission Line Termination (ZO = 50 Ω)

ADF4377 Output Networks

The differential outputs of the ADF4377 are designed to interface

with most differential signal devices while driving transmission lines

with far-end termination. Figure 98, Figure 99, and Figure 100

shows ac-coupled output configurations. Note that some receiver

devices have the 100 Ω termination resistor internal to the device,

in which case the external 100 Ω resistor is unnecessary. The

ADF4377 also interfaces with single-ended 50 Ω end terminations.

In this case, the unused output requires an ac-coupled 50 Ω termi-

nation. For the single-ended example in Figure 100, the CLKxP and

CLKxN pins may be swapped.

Figure 98. Common Clock Interface: Differential Clock with On Board End

Termination (ZO = 50 Ω)

Figure 99. Common Clock Interface: Differential Clock with On-Chip End

Termination (ZO = 50 Ω)

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