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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4377 датащи(PDF) 31 Page - Analog Devices |
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ADF4377 датащи(HTML) 31 Page - Analog Devices |
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31 / 79 page  Data Sheet ADF4377 THEORY OF OPERATION analog.com Rev. 0 | 31 of 79 because REG0010 triggers the VCO calibration and loading of all double buffers and, therefore, must be the last SPI register written to. The SINGLE_INSTRUCTION bit disables streaming mode when it is set to 1. When SINGLE_INSTRUCTION is set to 0, streaming mode is enabled. Block Power Down Control The power down control bits of the ADF4377 reside in REG0019 and REG001A. The PD_ALL, PD_RDET, PD_CLKOUT1, and PD_CLKOUT2 bits may be programmed independently. The PD_CLK, PD_CALDAC, PD_RDIV, PD_NDIV, PD_VCO, PD_LD, and PD_PFDCP bits must be set to the same state at all times. The only time this group is allowed to be set to 1 is when a full power-down ambient temperature measurement is performed (see Table 23). In all other cases, this bit grouping must be set to 0. Figure 79. Serial Interface, Recommended Streaming Mode (SINGLE_INSTRUCTION = 0) with Decrementing Registers (ADDRESS_ASCENCION = 0) |
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