ADF4377 datasheet(59/79 Pages) AD

59 / 79 page

Data Sheet

ADF4377

analog.com

Rev. 0 | 59 of 79

Address: 0x1B, Reset: 0x00, Name: REG001B

Figure 129.

Table 66. Bit Descriptions for REG001B

Bits

Bit Name

Description

Reset

Access

EN_LOL

Enable Loss-of-Lock Detector.

0x0

R/W

0: disabled.

1: enabled. Normal operation.

LDWIN_PW

Lock Detector Pulse Window.

0x0

R/W

0: narrow window. Normal operation.

1: wide window. Refer to the Lock Detector section.

EN_LDWIN

Enable the Lock Detector Pulse Window.

0x0

R/W

0: disabled.

1: enabled. Normal operation.

[4:0]

LD_COUNT

Number of Valid PFD Cycles Before the Lock Detector Indicates PLL is Locked. Refer to the Lock Detector

section.

0x0

R/W

Address: 0x1C, Reset: 0x00, Name: REG001C

Figure 130.

Table 67. Bit Descriptions for REG001C

Bits

Bit Name

Description

Reset

Access

EN_DNCLK

Enable VCO Calibration Divider. See Figure 70.

0x0

R/W

0: disabled. Disable when not in use to reduce spurious content.

1: enabled. Enable before a VCO calibration begins.

EN_DRCLK

Enable Divider to the VCO Calibration Block and ADC Clock Divider. See Figure 70.

0x0

R/W

0: disabled. Disable when not in use to reduce spurious content.

1: enabled. Enable before a VCO calibration or temperature sensor measurement begins.

R01C_RSV4

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R01C_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R01C_RSV2

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

RST_LD

Reset Lock Detector to the Unlocked State. This bit is not self-clearing.

0x0

R/W

0: reset inactive. Normal operation.

1: reset active.

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