ADF4377 datasheet(38/79 Pages) AD

38 / 79 page

Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 38 of 79

Table 33. SPI Summary - SPI Protocol

Bit Field

Value

MAIN_READBACK_CONTROL

0x0

Remaining Register Settings

The Charge Pump Test Mode section,MUXOUT section, and Block

Power Down Control section list several bit fields that are rec-

ommended for special purposes, such as debug or ambient die

temperature measurements. For this normal use case, these bit

fields must be set to their POR state (see Table 34). SOFT_RESET,

SOFT_RESET_R, RST_SYS, and ADC_ST_CNV are the only re-

maining RW bit fields not mentioned yet, and must also be set to

their POR state (see Table 34).

The bit columns in Table 42 have several cells without a name.

These unnamed, reserved cells must be programmed to the state

provided in Table 42 for proper operation.

Table 34. SPI Summary, Remaining Registers

Bit Field

Value

EN_CPTEST

0x0

CP_UP

0x0

CP_DOWN

0x0

MUXOUT

0x0

PD_CLK

0x0

PD_CALDAC

0x0

PD_ALL

0x0

PD_RDIV

0x0

PD_NDIV

0x0

PD_VCO

0x0

PD_LD

0x0

PD_PFDCP

0x0

SOFT_RESET, SOFT_RESET_R

0x0

RESET_SYS

0x0

ADC_ST_CNV

0x0

Programming Procedure

There are two different methods to power up the ADF4377. The

most commonly used method provided in the Standard Power-Up

and Initialization Sequence, Automatic VCO Calibration section is

mandatory on the initial device power-up.

The method provided in the Fast Power-Up and Initialization, Man-

ually Programmed VCO Calibration Settings (Optional) section is an

optional power-up procedure after the initial power-up.

Standard Power-Up and Initialization

Sequence, Automatic VCO Calibration

The following standard power-up and initialization sequence is the

recommended procedure to power up and program the ADF4377:

1. Follow Step 1 through Step 5 in the Power-Up and Initialization

Sequence section, using the register settings provided in the

Design Procedure section.

2. It is optional to monitor the status of the VCO calibration bit

fields, ADC_BUSY and FSM_BUSY. A VCO calibration is com-

pleted when ADC_BUSY transitions from high to low, followed

by FSM_BUSY transitioning from high to low. Typical automatic

VCO calibration times range from 3 ms to 9 ms.

3. After the VCO calibration is complete, disable the VCO

calibration clocks by setting EN_DRCLK = EN_DNCLK =

EN_ADC_CLK = 0. Disabling the VCO calibration clocks re-

duces the V3.3V_1 current by roughly 15 mA and reduces

unwanted spurious content.

4. PLL is locked when the lock detector sets the LKDET pin and

the LOCKED bit high.

Fast Power-Up and Initialization, Manually

Programmed VCO Calibration Settings

(Optional)

The purpose of the fast power-up and initialization method is to

avoid the automatic VCO calibration time, which is typically 3 ms to

9 ms. For fixed clock frequency converter applications, such as this

design and programming Example 1, automatic VCO calibration

times are typically acceptable. The following list provides the steps

to record the VCO calibration results on the initial power-up and

manually program VCO Calibration settings on subsequent power

ups:

1. On initial power, follow the procedure in the Standard Power-Up

and Initialization Sequence, Automatic VCO Calibration section.

2. Record calibration results from the VCO_CORE, VCO_BAND,

and VCO_BIAS bit fields and store the recorded results in

memory. Note that each unique device and frequency com-

bination generates different VCO_CORE, VCO_BAND, and

VCO_BIAS values.

3. Subsequent power-up and initialization sequences (see the-

Power-Up and Initialization Sequence section) can bypass the

automatic VCO calibration procedure by programming the over-

ride (O_VCO_CORE, O_VCO_BAND, and O_VCO_BIAS) and

manual (M_VCO_CORE, M_VCO_BAND, and M_VCO_BIAS)

VCO register bits with the register settings provided in Table 35.

All other bit fields from the Design Procedure section remain the

same.

Table 35. Manually Programmed VCO Calibration Settings

Bit Fields

Value

EN_AUTOCAL

0x0

EN_DRCLK

0x0

EN_DNCLK

0x0

EN_ADC_CLK

0x0

O_VCO_CORE

0x1

O_VCO_BAND

0x1

O_VCO_BIAS

0x1

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